Two-mode driver circuit

Claim 2

For connection to an MOS inverter circuit having an input terminal, an output terminal, first and second power terminals for connection to first and second reference voltage supplies respectively, a circuit comprising: a pair of MOS transistors connected in parallel between one of said first and second power terminals and one of said first and second reference voltage supplies, said first MOS transistor having its gate electrode connected to a third terminal, said second MOS transistor having its gate connected to its source or drain region for diode operation and having a channel width much smaller than channel width of said first MOS transistor; whereby the output terminal voltage swing of said MOS inverter circuit operation is reduced when a signal on said third terminal turns off said first MOS transistor.

Claim 3

A circuit as in claim 1 wherein said inverter circuit is a CMOS inverter circuit.

Claim 4

A circuit as in claim 2 wherein said first reference voltage supply is at a higher voltage than said second reference voltage supply and said MOS transistor pair are connected between said first reference voltage supply and said first power terminal.

Claim 5

A circuit as in claim 3 wherein said MOS transistor pair are PMOS transistors.

Claim 6

A circuit as in claim 2 wherein said first reference voltage supply is at a higher voltage than said second reference voltage supply and said MOS transistor pair are connected between said second reference voltage supply and said second power terminal.

Claim 7

A circuit as in claim 5 wherein said MOS transistor pair are NMOS transistors.

Claim 8

A circuit as in claim 1 further comprising a third MOS transistor connected in parallel to said first MOS transistor.

Claim 9

A CMOS driver circuit having first and second power terminals for connection to first and second reference voltage supplies respectively, an input terminal and an output terminal, comprising: first and second MOS output transistors, each MOS output transistor having first and second source/drain terminals and a gate terminal, said first source/drain terminal of said first MOS output transistor connected to said first power terminal, said second source/drain terminal of said first MOS output transistor connected to said driver circuit output terminal and to said first drain source/drain terminal of said second MOS output transistor, and said second source/drain terminal of said second MOS output transistor connected to said second power terminal; a first and second CMOS inverter, each having first and second power terminals for connection to said first and second reference voltage supplies respectively, an input terminal and an output terminal, said input terminals of both CMOS inverters connected to said driver circuit input terminal, said output terminal of said first CMOS inverter connected to said gate terminal of said first MOS output terminal, said output terminal of said second CMOS inverter connected to said gate terminal of said second MOS output terminal; means, having a third terminal and connected between one of said first and second power terminals each of said CMOS inverters and one of said first and second reference voltage supplies, for reducing the output terminal voltage swing of said CMOS inverter responsive to a signal on said third terminal.

Claim 10

A CMOS driver circuit having first and second power terminals for connection to first and second reference voltage supplies respectively, an input terminal and an output terminal, comprising: first and second MOS output transistors, each MOS output transistor having first and second source/drain terminals and a gate terminal, said first source/drain terminal of said first MOS output transistor connected to said first power terminal, said second source/drain terminal of said first MOS output transistor connected to said driver circuit output terminal and to said first drain source/drain terminal of said second MOS output transistor, and said second source/drain terminal of said second MOS output transistor connected to said second power terminal; a first and second CMOS inverter, each having first and second power terminals for connection to said first and second reference voltage supplies respectively, an input terminal and an output terminal, said input terminals of both CMOS inverters connected to said driver circuit input terminal, said output terminal of said first CMOS inverter connected to said gate terminal of said first MOS output terminal, said output terminal of said second CMOS inverter connected to said gate terminal of said second MOS output terminal; means, having a third terminal and connected between one of said first and second power terminals each of said CMOS inverters and one of said first and second reference voltage supplies, for reducing the output terminal voltage swing of said CMOS inverter responsive to a signal on said third terminal.

Claim 11

A CMOS driver circuit as in claim 8 wherein said output voltage swing reducing means comprises first and second MOS transistors connected in parallel between one of said first and second power terminals and one of said first and second reference voltage supplies, said first MOS transistor having its gate electrode connected to said third terminal, said second MOS transistor having its gate electrode connected to its source or drain region for diode operation, and having a channel width much smaller than that of said first MOS transistor; and whereby said driver circuit operation is slowed when a signal on said third terminal turns off said first MOS transistor.

Claim 12

A plurality of said CMOS driver circuits as in claim 9 on an integrated circuit, said third terminals of said CMOS driver circuits connected to an input pad whereby operations of all of said CMOS driver circuits are slowed by a signal on said input pad.

Claim 13

A CMOS driver circuit as in claim 9 wherein: said first reference voltage supply is at a higher voltage that said second reference voltage supply; said first CMOS inverter having its first and second MOS transistor connected in parallel between said first reference voltage supply and said first power terminal, and said channel regions of said first and second MOS transistors being of a first polarity type; and said second CMOS inverter having its first and second MOS transistors connected in parallel between said second reference voltage supply and said power terminal, and said channel regions of said first and second MOS transistors being of a second polarity type.

Claim 14

A CMOS driver circuit as in claim 11 wherein said first and second transistors of said first CMOS inverter are NMOS transistors and said first and second transistors of said second CMOS inverter are PMOS transistors.

Claim 15

A CMOS driver circuit as in claim 9 wherein said third terminal is connected to said output terminal whereby said driver circuit is partially slowed by feedback action from said output terminal to said first MOS transistor.

Claim 16

A CMOS driver circuit as in claim 9 further comprising: first switching means, having a control terminal, between each of said output terminals of said CMOS inverters and said gate terminal of said MOS output transistors respectively for decoupling said CMOS inverter output terminal from said gate terminal upon a signal to said control terminal, said control terminal connected to a fourth input terminal; second switching means, having a control terminal, for connecting each of said gate terminals of said MOS output transistors to said one of said reference voltage supplies respectively upon a signal to said control terminal, said control terminal connected to said fourth input terminal; whereby said CMOS driver circuit is placed into a high impedance state upon a signal on said fourth input terminal.

Claim 17

An integrated circuit having at least one input pad and a plurality of CMOS driver circuits as in claim 14, each fourth input terminal of said driver circuits connected to said input pad whereby a signal on said input terminal places all of said CMOS driver circuits into a high impedance state.

Claim 18

The CMOS driver circuit as in claim 14 wherein said first switching means comprises a pair of MOS transistors of opposing polarity, each MOS transistor having a first source/drain region connected to said output terminal of said CMOS inverter, a second source/drain region connected to said gate terminal of said MOS output terminal and a gate terminal connected to said fourth input terminal.

Claim 19

The CMOS driver circuit as in claim 14 wherein said second switching means comprises an MOS transistor having a first source/drain region connected to said reference voltage supply, a second source/drain region connected to said gate terminal of said MOS output transistor and a gate terminal connected to said fourth input terminal.

Claim 20

The CMOS driver circuit as in claim 14 further comprising a logic gate having an output terminal connected to said fourth input terminal and at least two input terminals.

Claim 21

An integrated circuit having at least one input pad and a plurality of CMOS driver circuits as in claim 16 wherein one of said two input terminals is connected to said input pad whereby a signal on said input pad places all of said CMOS driver circuits into a high impedance state.

Claim 22

The CMOS driver circuit as in claim 9 further comprising a third MOS connected in parallel with said first MOS transistor.