Semiconductor memory device with redundancy circuit

Claim 1

A semiconductor memory device comprising: an address buffer connected to receive an address signal; a main row decoder controlled in response to an output of said address buffer; main row lines selectively driven by an output of said main row decoder; main memory cells connected to said main row lines; at least one spare memory cell which is used instead of at least one of said main memory cells if it is defective; a spare row decoder for selecting the spare memory cell includes redundancy address setting means for determining whether or not said spare memory cell is to be used in response to an input address, and a buffer circuit connected to the spare memory cell; de-activating means, for setting said main row decoder into a nonoperable condition when said spare memory cell is selected, is controlled by said redundancy address setting means; programming means for applying a high voltage to said main and spare row lines; and discharging means for discharging the main and spare row lines for a preset period of time after the programming operation with respect to said main or spare memory cells is effected by said programming means, said buffer circuit being controlled by said discharging means and said redundancy address setting means.