Patent US4857776A successfully refreshed from Google Patents.
US4857776A
Expired / Lapsed
US
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True TTL output translator-driver with true ECL tri-state control
Assignee: Tandem Computers Inc
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Filing: 1987-11-20
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Granted: 1989-08-15
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Expires: 2007-11-20
Abstract
Abstract The present invention provdes a circuit for driving a TTL bus from an ECL circuit. The circuit of the present invention speeds up the "tri-state" to "active" transition by eliminating the need to pass the tri-state signal through a translator and buffer. A tri-state control circuit accepts true ECL input directly, thus eliminating the delay, power and density "cost" of the translator and buffer circuits. This circuit further improves the delay performance of tri-state/active transitions by restricting device saturation to low levels.
Inventors
- 👤 Aurangzeb K. Khan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:30
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/018; H03K19/01806; H03K19/01812; H03K19/01; H03K19/013; H03K19/02; H03K19/08; H03K19/082; H03K19/0823; H03K19/0826
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
401 words
A circuit for translating true ECL input signals, which have a HIGH state and a LOW state, and true ECL tri-state control signals, which have a HIGH state and a LOW state, to true TTL tri-state output signals which have a HIGH state, a LOW state, and a high impedance state, the circuit comprising: (a) a translator means for translating said true ECL input signals which have a HIGH state and a LOW state to corresponding true TTL signals which have a HIGH state and a LOW state; (b) an output driver means for receiving said true TTL signals which have a HIGH state and a LOW state from said translator means and generating corresponding true TTL tri-state output signals which have a HIGH state and a LOW state, the output driver means comprising: (i) a first output transistor capable of generating a true TTL signal with a HIGH state and capable of holding a high impedance state; and (ii) a second output transistor coupled to said first output transistor generating a true TT: signal with a LOW state and capable of holding a high impedance state; and (c) a tri-state controller means coupled to the output driver means and connected to receive the true ECL tri-state control signals for switching the output driver means into a true TTL tri-state high impedance state based on said true ECL tri-state control signals without converting said true ECL tri-state control signals into TTL tri-state control signals, the tri-state controller means comprising: (i) a comparator for comparing a true ECL tri-state control signal with a reference signal and providing a comparison signal if the control signal is in a HIGH state; and (ii) a controller electrically coupled to the first output transistor, the second output transistor, and the comparator, for causing the first output transistor to generate a true TTL signal with a HIGH state if the true TTL signal received from the translator is in a HIGH state an the comparator is not providing a comparison signal, for causing the second output transistor to generate a true TTL signal with a LOW state if the true TTL signal received from the translator is in a LOW state and the comparator is not providing a comparison signal, and for causing both the first output transistor and the second output transistor to enter a high impedance state if the comparator is providing a comparison signal.
Claim 2
Dependent Claim
401 words
A circuit for translating true ECL input signals, which have a HIGH state and a LOW state, and true ECL tri-state control signals, which have a HIGH state and a LOW state, to true TTL tri-state output signals which have a HIGH state, a LOW state, and a high impedance state, the circuit comprising: (a) a translator means for translating said true ECL input signals which have a HIGH state and a LOW state to corresponding true TTL signals which have a HIGH state and a LOW state; (b) an output driver means for receiving said true TTL signals which have a HIGH state and a LOW state from said translator means and generating corresponding true TTL tri-state output signals which have a HIGH state and a LOW state, the output driver means comprising: (i) a first output transistor capable of generating a true TTL signal with a HIGH state and capable of holding a high impedance state; and (ii) a second output transistor coupled to said first output transistor generating a true TT: signal with a LOW state and capable of holding a high impedance state; and (c) a tri-state controller means coupled to the output driver means and connected to receive the true ECL tri-state control signals for switching the output driver means into a true TTL tri-state high impedance state based on said true ECL tri-state control signals without converting said true ECL tri-state control signals into TTL tri-state control signals, the tri-state controller means comprising: (i) a comparator for comparing a true ECL tri-state control signal with a reference signal and providing a comparison signal if the control signal is in a HIGH state; and (ii) a controller electrically coupled to the first output transistor, the second output transistor, and the comparator, for causing the first output transistor to generate a true TTL signal with a HIGH state if the true TTL signal received from the translator is in a HIGH state an the comparator is not providing a comparison signal, for causing the second output transistor to generate a true TTL signal with a LOW state if the true TTL signal received from the translator is in a LOW state and the comparator is not providing a comparison signal, and for causing both the first output transistor and the second output transistor to enter a high impedance state if the comparator is providing a comparison signal.
Claim 3
Dependent Claim
11 words
The circuit of claim 1, wherein the controller comprises a transistor.
Claim 4
Dependent Claim
19 words
The circuit of claim 1, wherein the first transistor and the second transistor are connected in a totem-pole circuit.
Claim 5
Dependent Claim
342 words
A circuit for translating true ECL input signals, which have a HIGH state and a LOW state, and true ECL tri-state control signals, which have a HIGH state and a LOW state, to true TTL tri-state output signals which have a HIGH state, a LOW state, and a high impedance state, the circuit comprising: (a) a translator means for translating said true ECL input signals which have a HIGH state and a LOW state to corresponding true TTL signals which have a HIGH state and a LOW state, the translator means comprising: (i) a current source; (ii) an ECL input comparator coupled to said current source; and (iii) a stabilizing feedback means wherein the stabilizing feedback means is coupled to a TTL power source, a TTL ground, and the ECL input comparator, the stabilizing feedback means being comprised of a first NPN transistor, a second NPN transistor, a first resistor, and a second resistor, an emitter of the first transistor being connected to the TTL ground, a collector of the first transistor being connected to a first end of the first resistor and to a base of the second transistor, a base of the first transistor being connected to a first end of the second resistor, an emitter of the second transistor, and the ECL input comparator, a collector of the second transistor, a second end of the first resistor, and a second end of the second resistor being connected to the TTL power source; (b) an output driver means for receiving said true TTL signals which have a HIGH state and a LOW state from said translator means and outputting corresponding true TTL tri-state output signals which have a HIGH state and a LOW state; (c) a tri-state controller means coupled to the output driver means and connected to receive the true ECL tri-state control signals for switching the output driver means into a true TTL tri-state high impedance state based on said true ECL tri-state control signals without converting said true ECL tri-state control signals into TTL tri-state control signals.
Claim 6
Dependent Claim
342 words
A circuit for translating true ECL input signals, which have a HIGH state and a LOW state, and true ECL tri-state control signals, which have a HIGH state and a LOW state, to true TTL tri-state output signals which have a HIGH state, a LOW state, and a high impedance state, the circuit comprising: (a) a translator means for translating said true ECL input signals which have a HIGH state and a LOW state to corresponding true TTL signals which have a HIGH state and a LOW state, the translator means comprising: (i) a current source; (ii) an ECL input comparator coupled to said current source; and (iii) a stabilizing feedback means wherein the stabilizing feedback means is coupled to a TTL power source, a TTL ground, and the ECL input comparator, the stabilizing feedback means being comprised of a first NPN transistor, a second NPN transistor, a first resistor, and a second resistor, an emitter of the first transistor being connected to the TTL ground, a collector of the first transistor being connected to a first end of the first resistor and to a base of the second transistor, a base of the first transistor being connected to a first end of the second resistor, an emitter of the second transistor, and the ECL input comparator, a collector of the second transistor, a second end of the first resistor, and a second end of the second resistor being connected to the TTL power source; (b) an output driver means for receiving said true TTL signals which have a HIGH state and a LOW state from said translator means and outputting corresponding true TTL tri-state output signals which have a HIGH state and a LOW state; (c) a tri-state controller means coupled to the output driver means and connected to receive the true ECL tri-state control signals for switching the output driver means into a true TTL tri-state high impedance state based on said true ECL tri-state control signals without converting said true ECL tri-state control signals into TTL tri-state control signals.
Claim 7
Dependent Claim
392 words
A circuit for translating true ECL input signals, which have a HIGH state and a LOW state, and true ECL tri-state control signals, which have a HIGH state and a LOW state, to true TTL tri-state output signals which have a HIGH state, a LOW state, and a high impedance state, the circuit comprising: (a) a translator means for translating said true ECL input signals which have a HIGH state and a LOW state to corresponding true TTL signals which have a HIGH state and a LOW state; (b) an output driver means for receiving said true TTL signals which have a HIGH state and a LOW state from said translator means and outputting corresponding true TTL tri-state output signals which have a HIGH state and a LOW state; and (c) a tri-state controller means coupled to the output driver means and connected to receive the true ECL tri-state control signals for switching the output driver means into a true TTL tri-state high impedance state based on said true ECL tri-state control signals without convection said true ECL tri-state control signals into TTL tri-state control signals, the tri-state controller means being coupled to the translator means, a TTL power source, a TTL ground, and an ECL power source, the tri-state controller means being comprised of a tri-state input comparator connected to the ECL power source and the TTL ground, a first end of a first resistor being connected to a TTL power source, a second end of the first resister being connected to a collector and a base of a first transistor, an emitter of the first transistor being connected to a base of a second transistor and to a collector and a base of a third transistor, a collector of the second transistor being connected to the TTL power source, an emitter of the second transistor being connected to the output driver means, to the tri-state input comparator, and to a collector of a fourth transistor, an emitter of the third transistor being connected to a first end of a schottky diode, a second end of the shcottky diode being connected to the TTL ground, a base of the fourth transistor being connected to the translator means and to a first end of a second resistor, and a second end of the second resistor being connected to the TTL power source.
Claim 8
Dependent Claim
392 words
A circuit for translating true ECL input signals, which have a HIGH state and a LOW state, and true ECL tri-state control signals, which have a HIGH state and a LOW state, to true TTL tri-state output signals which have a HIGH state, a LOW state, and a high impedance state, the circuit comprising: (a) a translator means for translating said true ECL input signals which have a HIGH state and a LOW state to corresponding true TTL signals which have a HIGH state and a LOW state; (b) an output driver means for receiving said true TTL signals which have a HIGH state and a LOW state from said translator means and outputting corresponding true TTL tri-state output signals which have a HIGH state and a LOW state; and (c) a tri-state controller means coupled to the output driver means and connected to receive the true ECL tri-state control signals for switching the output driver means into a true TTL tri-state high impedance state based on said true ECL tri-state control signals without convection said true ECL tri-state control signals into TTL tri-state control signals, the tri-state controller means being coupled to the translator means, a TTL power source, a TTL ground, and an ECL power source, the tri-state controller means being comprised of a tri-state input comparator connected to the ECL power source and the TTL ground, a first end of a first resistor being connected to a TTL power source, a second end of the first resister being connected to a collector and a base of a first transistor, an emitter of the first transistor being connected to a base of a second transistor and to a collector and a base of a third transistor, a collector of the second transistor being connected to the TTL power source, an emitter of the second transistor being connected to the output driver means, to the tri-state input comparator, and to a collector of a fourth transistor, an emitter of the third transistor being connected to a first end of a schottky diode, a second end of the shcottky diode being connected to the TTL ground, a base of the fourth transistor being connected to the translator means and to a first end of a second resistor, and a second end of the second resistor being connected to the TTL power source.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-08-14 | 1993-02-13 | 1993-08-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-08-14 | 1997-02-13 | 1997-08-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-08-14 | 2001-02-13 | 2001-08-15 | $7700.00 | Window Closed / Lapsed |