Method of manufacturing a semiconductor memory device

Claim 1

A method of manufacturing a semiconductor memory device comprising a memory element area formed by a plurality of bipolar transitors in a first area of a first conductivity type semiconductor substrate and a peripheral circuit area formed by a plurality of circuit elements in a second area of said semiconductor substrate, said method comprising: a first step of preparing said semiconductor substrate; a second step of forming a second conductivity type subcollector layer on said semiconductor substrate; a third step of forming a second conductivity type collector layer on said second conductivity type subcollector layer; a fourth step of simultaneously forming first and second insulation layers in a region corresponding to said memory element are and regions corresponding to prescribed regions of said peripheral circuit area within an upper layer part of said second conductivity type collector layer; a fifth step of selectively removing said first insulation layer; and a sixth step of isolating regions for forming said plurality of bipolar transistors from each other and isolating regions for forming said plurality of circuit elements from each other respectively by a trench isolation process.

Claim 2

A method of manufacturing a semiconductor memory device comprising a memory element area formed by a plurality of bipolar transitors in a first area of a first conductivity type semiconductor substrate and a peripheral circuit area formed by a plurality of circuit elements in a second area of said semiconductor substrate, said method comprising: a first step of preparing said semiconductor substrate; a second step of forming a second conductivity type subcollector layer on said semiconductor substrate; a third step of forming a second conductivity type collector layer on said second conductivity type subcollector layer; a fourth step of simultaneously forming first and second insulation layers in a region corresponding to said memory element are and regions corresponding to prescribed regions of said peripheral circuit area within an upper layer part of said second conductivity type collector layer; a fifth step of selectively removing said first insulation layer; and a sixth step of isolating regions for forming said plurality of bipolar transistors from each other and isolating regions for forming said plurality of circuit elements from each other respectively by a trench isolation process.