Abstract Disclosed herein is a method and circuit useful in the testing of integrated circuit chips. On-chip test circuitry is provided at a selected location on an IC chip and energized while the chips are still mounted on a lead frame member, wound on reels and heated in an oven. Advantageously, the continuous lead frame member may be a tape automated bond (TAB bond) flexible circuit which is adapted for gang bonding to a large plurality of ICs before being wound on reels. In a preferred test circuit embodiment, the conductive on-off state of digital address circuitry is controlled by applying a test signal potential to an input test pad and through a fuse to a common test circuit junction. This junction is in turn connected between a transistor and diode in a series control network which is operative to control the conductive state of the address circuitry. This network enables the input test pad to be used as both a test signal input connection and a ground connection for the IC test circuit.
A process for burning in an integrated circuit which includes: a. mounting a plurality of integrated circuit chips on a continuous lead frame, b. heating said chips to a predetermined elevated temperature, and c. cycling said chips with test vector signals generated from individual on-chip circuitry by electrically energizing all of said chips simultaneously through said continuous lead frame for a predetermined time and at said elevated temperature to accomplish burn-in thereof without the requirement for individually mounting said chips on burn-in carriers.
Claim 2
Dependent Claim
83 words
A process for burning in an integrated circuit which includes: a. mounting a plurality of integrated circuit chips on a continuous lead frame, b. heating said chips to a predetermined elevated temperature, and c. cycling said chips with test vector signals generated from individual on-chip circuitry by electrically energizing all of said chips simultaneously through said continuous lead frame for a predetermined time and at said elevated temperature to accomplish burn-in thereof without the requirement for individually mounting said chips on burn-in carriers.
Claim 3
Dependent Claim
80 words
A process for testing integrated circuits which comprises: a bonding said integrated circuits to a continuous flexible lead frame member, b. winding said lead frame member onto a reel, c. heating said integrated circuits at a predetermined elevated temperature for a predetermined time, d. generating a plurality of test drive signals simultaneously from a common voltage supply, and e. applying said test drive signals to said integrated circuits while said integrated circuits are all being simultaneously heated on said reel.
Claim 4
Dependent Claim
80 words
A process for testing integrated circuits which comprises: a bonding said integrated circuits to a continuous flexible lead frame member, b. winding said lead frame member onto a reel, c. heating said integrated circuits at a predetermined elevated temperature for a predetermined time, d. generating a plurality of test drive signals simultaneously from a common voltage supply, and e. applying said test drive signals to said integrated circuits while said integrated circuits are all being simultaneously heated on said reel.
Claim 5
Dependent Claim
47 words
The process defined in claim 2 wherein the application of a test signal includes: a. providing an on-chip test circuit segment on each integrated circuit, and b. energizing said on-chip test circuit by applying a DC bias voltage thereto and via said lead frame while being heated.