Arrangement for the individual adaptation of a serial interface of a data processing system to a data transmission speed of a communication partner

Claim 1

An arrangement for adapting a serial interface of a data processing system to a data transmission speed of data transmission signals from a communication partner, comprising: (a) recognition circuit means for recognizing said data transmission speed including: (i.) reference frequency generator means for generating a reference frequency signal; (ii.) counter means controlled by said data transmission signals from said communication partner for counting pulses of said reference frequency signal; (iii.) reading means in a microprocessor means for reading from said counter means a counting result of said counting of pulses; and (iv.) logic means for providing an adjustment division signal to an adjustment means based on said counting results; (b) said microprocessor means being connected to said recognition circuit means for controlling said recognition means; (c) clock frequency generating means connected to said microprocessor means for outputting a clock frequency signal to said microprocessor means; d) adjustment means for adjusting said frequency clock generating means to produce an adjusted clock frequency signal which corresponds to a matching data transmission speed which matches said data transmission speed wherein said adjustment means includes a phase locking loop including: (i.) voltage controlled oscillator means as said clock frequency generating means for generating said clock frequency signal; (ii.) first frequency divider means for dividing said clock frequency signal in a first division ratio equal to the inverse of the adjustment division signal; said first frequency divider means receiving said adjustment division signal from said microprocessor means; (iii.) phase comparator means for comparing said divided clock frequency signal with a divided reference frequency signal received from a second frequency divider outside said loop; and (iv.) a lowpass filter for filtering higher-frequency fractions from an output of said phase comparator means, and for providing the filtered output of said phase comparator to adjust said clock frequency signal of said voltage control oscillator so that said divided clock frequency signal of said voltage controlled oscillator equals said divided reference signal; and (e) derivation means in said microprocessor means for deriving said matching data transmission speed from said adjusted clock frequency signal.