Frequency sample-and-hold circuit

Claim 3

A signal generator comprising: a frequency sample-and-hold circuit in accordance with claim 1 for sampling an incoming reference signal and generating a secondary signal; a local oscillator; means for comparing said secondary signal frequency with a rational multiple of said local oscillator frequency and producing a voltage that is a function of the frequency difference therebetween; feedback means for utilizing said voltage to control the frequency of said oscillator; and signal generating means, responsive to the frequency of said local oscillator, for producing an output signal.

Claim 4

The signal generator according to claim 2 wherein said signal generating means comprises: an amplifier; a plurality of different feedback loops, each of whose delay time is controlled by said local oscillator; and switching means for selectively coupling a difference one of said feedback loops between the output and input ports of said amplifier thereby forming an oscillator.

Claim 5

In a communication system including a first transmission line for transmitting a signal to a distant station, and a second transmission line for receiving signals from said distant station, a frequency translating circuit disposed in said second transmission line comprising: a first frequency mixer for receiving a pair of input signals f 1 +Δ and f 2 +Δ and forming a difference frequency signal f 1 -f 2 , where Δ is a small number relative to f 1 and f 2 ; first and second frequency multipliers for multiplying said difference frequency signal and forming two signals having frequencies n(f 1 -f 2 ) and m(f 1 -f 2 ), where n and m are different integers; means for coupling said n(f 1 -f 2 ) hertz signal to a first frequency sample-and-hold circuit in accordance with claim 1 and producing a continuous output signal at frequency n(f 1 -f 2 ); means for coupling said m(f 1 -f 2 ) hertz signal to a second frequency mixer along with input signal f 1 +Δ to form a difference signal f 1 + Δ - m(f 1 -f 2 ); where f.sub.1 + Δ - m(f.sub.1 -f.sub.2) = n(f.sub.1 -f.sub.2) + Δ or ##EQU1## means for coupling said n(f 1 -f 2 ) + Δ hertz signal derived from said second mixer to a second frequency sample-and-hold circuit in accordance with claim 1 and producing a continuous output signal at frequency n(f 1 -f 2 ) + Δ; means for coupling said first frequency sample-and-hold circuit to a third frequency mixer along with a signal from a local oscillator to produce a first sum frequency output signal F + n(f 1 -f 2 ), where F is the frequency of said local oscillator; means for coupling said second frequency sample-and-hold circuit to a fourth frequency mixer along with a signal from said local oscillator to produce a second sum frequency output signal F + n(f 1 -f 2 ) + Δ; means for coupling said first sum frequency signal to a fifth frequency mixer disposed along said second transmission line for up-converting a received signal at a frequency f+Δ to a frequency n(f 1 -f 2 ) + f + Δ; and means for coupling said second sum frequency signal to a sixth frequency mixer along with said up-converted signal to produce a difference frequency output signal f.

Claim 6

A frequency sample-and-hold circuit for generating a secondary signal whose fundamental frequency is a function of the fundamental frequency of an incoming reference signal of limited time duration comprising: a clock signal source; means for counting and storing, during the duration of said reference signal, the number of cycles of said clock signal source occurring between zero crossings of said reference signal; and means for producing, following the termination of said reference signal; a secondary signal whose zero crossing intervals are substantially equal to a rational multiple of the stored count multiplied by a period of time defined by said clock source.

Claim 7

A frequency sample-and-hold circuit for generating a secondary signal whose fundamental frequency is a function of the fundamental frequency of an incoming reference signal of limited time duration comprising: a clock signal source; means for counting and storing, during the duration of said reference signal, the number of cycles of said clock signal source occurring between zero crossings of said reference signal; and means for producing, following the termination of said reference signal; a secondary signal whose zero crossing intervals are substantially equal to a rational multiple of the stored count multiplied by a period of time defined by said clock source.

Claim 8

A frequency sample-and-hold circuit comprising: a clock signal source; a counter; a register; means for coupling said clock signal source to said counter; means for sensing the presence of an incoming reference signal; means for generating a reset pulse at each zero crossing of said reference signal; means for coupling said reset pulse to said counter; means for transferring the accumulated count in said counter to said register coincident with the occurrence of each reset pulse; means for sensing the absence of an incoming reference signal; and means for generating a secondary signal whose fundamental frequence is a rational multiple of the fundamental frequency of said reference signal as defined by the count stored in said register.

Claim 9

A frequency sample-and-hold circuit comprising: a clock signal source; a counter; a register; means for coupling said clock signal source to said counter; means for sensing the presence of an incoming reference signal; means for generating a reset pulse at each zero crossing of said reference signal; means for coupling said reset pulse to said counter; means for transferring the accumulated count in said counter to said register coincident with the occurrence of each reset pulse; means for sensing the absence of an incoming reference signal; and means for generating a secondary signal whose fundamental frequence is a rational multiple of the fundamental frequency of said reference signal as defined by the count stored in said register.

Claim 10

The frequency sample-and-hold circuit according to claim 6 wherein said means for sensing the presence of an incoming reference signal comprises: a pair of full-wave rectifiers; means for coupling said reference signal to said rectifiers 90° out of time phase; means for summing the outputs from said pair of rectifiers; and means for amplifying and limiting the output signal from said summing means.

Claim 11

The frequency sample-and-hold circuit according to claim 7 wherein said means for generating a reset pulse comprises; a first AND gate; a second AND gate; means, including an inverter, for coupling the output from one of said rectifiers to one input port of said first AND gate; the other input port of said first AND gate being coupled to said clock source; means for coupling the output port of said first AND gate to one of the input ports of said second AND gate; and means for coupling the output from said amplifying and limiting means to the other input port of said second AND gate.

Claim 12

The frequency sample-and-hold circuit according to claim 7 wherein said means for sensing the absence of an incoming reference signal includes an inverter coupled to the output port of said amplifying and limiting means.

Claim 13

The frequency sample-and-hold circuit according to claim 6 wherein said means for transferring the accumulated count comprises: a plurality of AND gates; means for coupling each output port of said counter to one of the output ports of a different one of said plurality of AND gates; means for coupling said reset pulse generating means to the other input port of each of said plurality of AND gates; and means for coupling the output ports of said plurality of AND gates to the input ports of said register.

Claim 14

The frequency sample-and-hold circuit according to claim 6 wherein said means for transferring the accumulated count in said counter to said register includes an arithmetic processing unit for forming a rational multiple of said count.

Claim 15

The frequency sample-and-hold circuit according to claim 6 wherein said means for generating a secondary signal comprises: a plurality of coincidence gates, each one of which has one input port coupled to a different output port of said counter, and the other input port coupled to the corresponding port of said register; means for coupling the output ports of said coincidence gates to the output ports of a multiple AND gate; means for coupling the output port of said multiple AND gate to one of the input ports of an AND gate; means for coupling the other input port of said AND gate to said means for sensing the absence of an incoming reference signal; and a flip-flop circuit connected to the output port of said AND gate.