US3710262A
Expired / Lapsed
US
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Synchronized counting system for counting symmetrical signals during a time base
Assignee: Franklin Electric Co Inc
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Filing: 1971-11-02
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Granted: 1973-01-09
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Expires: 1991-11-02
Abstract
Abstract This disclosure deals with a system for counting the number of cycles of a symmetrical signal, occurring within a time base. The time base is initiated essentially in synchronism with a point in a cycle of the signal and it is terminated a predetermined time thereafter. A counter counts the cycles occurring during the time base and a count is registered at a second point in each cycle, the second point being displaced one-half cycle from the first point, thus providing an advantageous round-off feature.
Inventors
- 👤 P Sorensen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 16:33
CPC Classifications
G; G01; G01R; G01R23/00; G01R23/02; G01R23/10
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
93 words
A counting system for counting the number of cycles occurring during a time base signal of a substantially symmetrical signal, comprising circuit means responsive to said symmetrical signal for initiating a time base signal in synchronism with a predetermined point in a cycle of said symmetrical signal, gating means having inputs connected to receive said symmetrical signal and said time base signal, and counting means connected to receive the output of said gating means and to count in each cycle at another point which is displaced substantially one-half cycle from said predetermined point.
Claim 2
Dependent Claim
93 words
A counting system for counting the number of cycles occurring during a time base signal of a substantially symmetrical signal, comprising circuit means responsive to said symmetrical signal for initiating a time base signal in synchronism with a predetermined point in a cycle of said symmetrical signal, gating means having inputs connected to receive said symmetrical signal and said time base signal, and counting means connected to receive the output of said gating means and to count in each cycle at another point which is displaced substantially one-half cycle from said predetermined point.
Claim 3
Dependent Claim
25 words
A system as in claim 1, wherein said predetermined point comprises the beginning of a cycle, and said other point is midway in a cycle.
Claim 4
Dependent Claim
21 words
A counting system as in claim 1, wherein said circuit means generates a time base signal having a fixed time duration.
Claim 5
Dependent Claim
51 words
A counting system as in claim 1, wherein said circuit means comprises second counting means, oscillator means, and second gating means for connecting the output of said oscillator means to the input of said second counting means essentially in synchronism with said predetermined point in a cycle of said symmetrical signal.
Claim 6
Dependent Claim
24 words
A counting system as in claim 4, wherein the frequency of said oscillator means is substantially greater than the frequency of said symmetrical signal.
Claim 7
Dependent Claim
39 words
A counting system as in claim 1, wherein said circuit means is adapted to respond to a positive transition of a square wave and said counting means is adapted to respond to a negative transition of a square wave.
Claim 8
Dependent Claim
86 words
A signal synchronization circuit for providing a base signal in response to a start signal and to a regularly varying signal, comprising first circuit means for generating said base signal, said first circuit means including an enabling circuit which initiates said base signal in response to an enabling signal, and second circuit means responsive to said start signal and to said regularly varying signal for providing said enabling signal at a predetermined point in the first cycle of said varying signal occurring after a start signal.
Claim 9
Dependent Claim
86 words
A signal synchronization circuit for providing a base signal in response to a start signal and to a regularly varying signal, comprising first circuit means for generating said base signal, said first circuit means including an enabling circuit which initiates said base signal in response to an enabling signal, and second circuit means responsive to said start signal and to said regularly varying signal for providing said enabling signal at a predetermined point in the first cycle of said varying signal occurring after a start signal.
Claim 10
Dependent Claim
20 words
A circuit as in claim 7, wherein said first circuit means provides a base signal having a preselected time duration.
Claim 11
Dependent Claim
40 words
A circuit as in claim 8, wherein said first circuit means includes an oscillator, and a counter for counting cycles of said oscillator, said time duration being dependent upon the count of said counter and the frequency of said oscillator.
Claim 12
Dependent Claim
48 words
A circuit as in claim 9, wherein said first circuit means further includes a flip-flop connected to said counter and set by the first count of said counter and reset by the last count of said counter, said flip-flop providing said base signal while in said reset state.
Claim 13
Dependent Claim
27 words
A circuit as in claim 9, wherein said enabling circuit includes a gate connected between said oscillator and said counter, said enabling signal turning said gate on.
Claim 14
Dependent Claim
56 words
A circuit as in claim 11, wherein said first circuit means further comprises bistable means having an input connected to said counter and being toggled upon said counter reaching said last count, said bistable means further including an output connected to said enabling circuit for inhibiting said enabling circuit upon said toggling of said bistable means.
Claim 15
Dependent Claim
34 words
A circuit as in claim 7, wherein said second circuit means includes gate means connected to respond to said start signal and to said regularly varying signal, said gate means initiating said enabling signal.
Claim 16
Dependent Claim
62 words
A circuit as in claim 13, wherein said second circuit means further includes bistable means connected between said gate means and said enabling circuit, said bistable means being toggled to a first state by the beginning of the first cycle of said varying signal which occurs after said start signal, said bistable means forming said enabling signal when in said first state.
Claim 17
Dependent Claim
23 words
A circuit as in claim 14, wherein said bistable means is connected to be toggled to a second state by a start signal.
Claim 18
Dependent Claim
68 words
A circuit as in claim 13, wherein said second circuit further includes bistable means forming said connection between said start signal and said gate means, said bistable means being toggled to a first state by a start signal and thereby inhibiting said gate means, said bistable means being further connected to receive said varying signal and being toggled to a second state and thereby enabling said gate means.
Claim 19
Dependent Claim
52 words
A circuit as in claim 8, further including counting means, and gate means having its output connected to said counting means and two inputs respectively connected to said varying signal and to said output signal, said counting means counting the number of the other of said edges occurring within said time duration.
Claim 20
Dependent Claim
97 words
A circuit for counting to the nearest whole cycle the number of cycles of a regularly varying signal occurring during a base signal having a predetermined time duration, each of said cycles including a first point and a second point which is one-half cycle removed from said first point, said circuit comprising counter means adapted to receive said base signal and to initiate a counting operation in synchronism with one of said first points, and said counter means being connected to receive said varying signal and counting during said base signal the number of said second points.
Claim 21
Dependent Claim
97 words
A circuit for counting to the nearest whole cycle the number of cycles of a regularly varying signal occurring during a base signal having a predetermined time duration, each of said cycles including a first point and a second point which is one-half cycle removed from said first point, said circuit comprising counter means adapted to receive said base signal and to initiate a counting operation in synchronism with one of said first points, and said counter means being connected to receive said varying signal and counting during said base signal the number of said second points.
Claim 22
Dependent Claim
116 words
A circuit for counting to the nearest whole cycle the number of cycles of a regularly varying signal occurring during a predetermined time, each of said cycles including a first point and a second point which is 1/2 cycle removed from said first point, said circuit comprising time base means for generating a base signal having a time duration equal to said predetermined time, means responsive to said varying signal and connected to said time base means for initiating a base signal in synchronism with one of said first points, and counter means connected to receive both said base signal and said varying signal for counting during said base signal the number of said second points.
Claim 23
Dependent Claim
116 words
A circuit for counting to the nearest whole cycle the number of cycles of a regularly varying signal occurring during a predetermined time, each of said cycles including a first point and a second point which is 1/2 cycle removed from said first point, said circuit comprising time base means for generating a base signal having a time duration equal to said predetermined time, means responsive to said varying signal and connected to said time base means for initiating a base signal in synchronism with one of said first points, and counter means connected to receive both said base signal and said varying signal for counting during said base signal the number of said second points.
Claim 24
Dependent Claim
115 words
A circuit for counting to the nearest whole cycle the number of cycles of a regularly varying signal occurring during a predetermined time, each of said cycles including a first point and a second point which is one-half cycle removed from said first point, said circuit comprising means responsive to said varying signal for generating a time base initiation signal coincident with said first point in a cycle of said varying signal, means for generating a base signal having a predetermined time duration in response to said initiation signal, and counter means connected to receive both said base signal and said varying signal for counting during said base signal the number of said second points.
Claim 25
Dependent Claim
115 words
A circuit for counting to the nearest whole cycle the number of cycles of a regularly varying signal occurring during a predetermined time, each of said cycles including a first point and a second point which is one-half cycle removed from said first point, said circuit comprising means responsive to said varying signal for generating a time base initiation signal coincident with said first point in a cycle of said varying signal, means for generating a base signal having a predetermined time duration in response to said initiation signal, and counter means connected to receive both said base signal and said varying signal for counting during said base signal the number of said second points.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-01-09 | 1976-07-10 | 1977-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-01-09 | 1980-07-10 | 1981-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-01-09 | 1984-07-10 | 1985-01-09 | $7700.00 | Window Closed / Lapsed |