US4853757A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit
Assignee: Mitsubishi Electric Corp
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Filing: 1988-12-19
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Granted: 1989-08-01
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Expires: 2008-12-19
Abstract
Abstract A semiconductor integrated circuit such as a master slice LSI, wherein a gate region and input/output cell regions in the periphery thereof are composed entirely of logic-constituting elements servable as input/output cells. The logic-constituting cells in the whole of the input/output cell regions and any desired portion of the gate region are formed as input/output cells in the slice process of production.
Inventors
- 👤 Yoichi Kuramitsu
- 👤 Takahiko Arakawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 17:02
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/998
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
79 words
A large scale semiconductor integrated circuit comprising: a substrate; a gate region formed on said substrate; an I/O region formed at a periphery of said gate region; and a plurality of cell arrays formed in said gate region and said I/O region, the cell arrays in said gate region being formed as logic elements which can function as either of I/O cells and gate cells, some of the cell arrays in said gate region functioning as said I/O cells.
Claim 2
Dependent Claim
79 words
A large scale semiconductor integrated circuit comprising: a substrate; a gate region formed on said substrate; an I/O region formed at a periphery of said gate region; and a plurality of cell arrays formed in said gate region and said I/O region, the cell arrays in said gate region being formed as logic elements which can function as either of I/O cells and gate cells, some of the cell arrays in said gate region functioning as said I/O cells.
Claim 3
Dependent Claim
89 words
A large scale semiconductor integrated circuit comprising: a plurality of cell arrays formed on a chip; said cell arrays function as either of I/O cells and gate cells; some of said cell arrays, functioning as the I/O cells, forming a peripheral region of the chip, some others of said cell arrays, functioning as the gate cells, forming a gate region surrounded by said peripheral region; and at least one of the cell arrays, within the region in which gates cells are formed, being arranged to form the I/O cell.
Claim 4
Dependent Claim
89 words
A large scale semiconductor integrated circuit comprising: a plurality of cell arrays formed on a chip; said cell arrays function as either of I/O cells and gate cells; some of said cell arrays, functioning as the I/O cells, forming a peripheral region of the chip, some others of said cell arrays, functioning as the gate cells, forming a gate region surrounded by said peripheral region; and at least one of the cell arrays, within the region in which gates cells are formed, being arranged to form the I/O cell.
Claim 5
Dependent Claim
73 words
A large scale semiconductor integrated circuit comprising: a substrate; a gate region formed on said substrate; an I/O region formed at a periphery of said gate region; and a plurality of cell arrays formed in said gate region and said I/O region, said cell arrays in said gate region being formed as logic elements, said logic elements including a first group functioning as gate cells and a second group functioning as I/O cells.
Claim 6
Dependent Claim
73 words
A large scale semiconductor integrated circuit comprising: a substrate; a gate region formed on said substrate; an I/O region formed at a periphery of said gate region; and a plurality of cell arrays formed in said gate region and said I/O region, said cell arrays in said gate region being formed as logic elements, said logic elements including a first group functioning as gate cells and a second group functioning as I/O cells.
References Cited (Backward Citations)
US3577038A
Cited
DE3147932A1
Cited
JPS58116757A
Cited
EP0098163A2
Cited
JPS59220948A
Cited
US4668972A
Cited
EP0189183A1
Cited
JPH0634036A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-31 | 1993-01-30 | 1993-08-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-31 | 1997-01-30 | 1997-08-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-31 | 2001-01-30 | 2001-08-01 | $7700.00 | Window Closed / Lapsed |