Digital crossbar switch

Claim 2

A digital crossbar switch for switching data between an internal data bus and one or more input/output data buses, comprising: a plurality of multiplexer logic units; an m-bit internal data bus coupled to each of said multiplexer logic units where m is an integer; a plurality of n-bit input/output data buses, one connected to each of said multiplexer logic units where n is an integer; a m/n to 1 multiplexer, where m/n is an integer, each multiplexer logic unit having an input coupled to said internal data bus and an output coupled to a corresponding one of said input/output data buses and operative in response to a configuration control signal to switch a selected n-bits of data from said internal data bus to the corresponding input/output data bus; and memory storage for configuration control signals coupled to said m/n to 1 multiplexer.

Claim 3

A switch according to claim 1, wherein at least a portion of said memory storage is programmable.

Claim 4

A switch according to claim 1, including a control input/output unit coupled to each of said multiplexer logic units

Claim 5

A switch according to claim 1, including an input data register coupled to said input/output data bus in each of said multiplexer logic units for storing input data therein and inputting said data at a selected subsequent time.

Claim 6

A switch according to claim 4, including an input multiplexer in each of said multiplexer logic units having one input connected to a corresponding input/output data bus and another connected to an output of said input data register and operative in response to a control signal to select either real time input or input from said input data register.

Claim 7

A switch according to claim 3, including a multiplexer in each of said multiplexer logic units having a first input connected to said internal data bus and a second input connected to said control input/output unit.

Claim 8

A switch according to claim 6, including a multiplexer coupled to said memory storage for reading out control words stored therein.

Claim 9

A switch according to claim 2, wherein said memory storage includes a bank of programmable flip-flops.

Claim 10

A switch according to claim 1, wherein said memory storage includes a preselected permanent control word.

Claim 11

A switch according to claim 1, wherein said memory storage includes permanent control words for transceiver and read-back functions.

Claim 12

A digital crossbar switch, for transferring data between an internal data bus and one or more input/output data buses, comprising: an internal data bus; a plurality of multiplexer logic units each coupled to said internal data bus; a plurality of input/output data buses, one being coupled to each of said multiplexer logic units, wherein number of bits in each of said input/output data buses is "n" and the total number of bits in all of said input/output data buses equals "m", the number of bits in said internal data bus; a control input/output unit coupled to each of said multiplexer logic units for controlling the transfer of configuration control bits into and out of said multiplexer logic units; a logic controller coupled to each of said multiplexer logic units for transmitting logic control signals into said multiplexer logic units; a data input controller coupled to a corresponding data bus an in response to selected control signals to pass input data to said internal data bus; a data output controller in each of said multiplexer logic units coupled to said internal data bus for selectively transmitting n bits of data from said internal data bus to an input/output data bus of an associated multiplexer logic unit in accordance with a selected control word; and control word memory coupled to said data output controller for storing switching configuration instructions and applying a selected control word in accordance with a selected logic signal from said logic controller.

Claim 13

A digital crossbar switch, for transferring data between an internal data bus and one or more input/output data buses, comprising: an internal data bus; a plurality of multiplexer logic units each coupled to said internal data bus; a plurality of input/output data buses, one being coupled to each of said multiplexer logic units, wherein number of bits in each of said input/output data buses is "n" and the total number of bits in all of said input/output data buses equals "m", the number of bits in said internal data bus; a control input/output unit coupled to each of said multiplexer logic units for controlling the transfer of configuration control bits into and out of said multiplexer logic units; a logic controller coupled to each of said multiplexer logic units for transmitting logic control signals into said multiplexer logic units; a data input controller coupled to a corresponding data bus an in response to selected control signals to pass input data to said internal data bus; a data output controller in each of said multiplexer logic units coupled to said internal data bus for selectively transmitting n bits of data from said internal data bus to an input/output data bus of an associated multiplexer logic unit in accordance with a selected control word; and control word memory coupled to said data output controller for storing switching configuration instructions and applying a selected control word in accordance with a selected logic signal from said logic controller.

Claim 14

A switch according to claim 11, wherein said data output controller is an m/n to 1 multiplexer.

Claim 15

A switch according to claim 12, including a source selector switch having an output coupled to an input of said control word memory and inputs coupled to said internal data bus and to said control input/output unit and operative in response to a selected source logic signal to select data to be stored in said memory from either said internal data bus or said control input/output unit.

Claim 16

A switch according to claim 11, including a memory output controller coupled to said memory and to said logic controller for transmitting memory control words selected in response to control signals from said logic controller.

Claim 17

A switch according to claim 11, including an input data buffer having an input coupled to said input/output data bus and an output coupled to said input multiplexer for storing input data for later transmission through said input multiplexer.

Claim 18

A switch according to claim 11, including an isolator coupled to an output of said m/n to 1 multiplexer and having an output connected to said input/output data bus in each of said multiplexer logic units.

Claim 19

A switch according to claim 11, wherein said control word memory includes a bank of programmable flip-flops.

Claim 20

A switch according to claim 15, wherein said input data buffer is a register.

Claim 21

A switch according to claim 13, including a data input buffer for temporarily storing input data from said input/output data bus and said data input controller and said selector switch operative in response to selected control signals to obtain control words for storage in control word memory from either data input on said input/output data bus or from said control input/output unit.

Claim 22

A switch according to claim 11, including a clock signal for controlling the transmission of data through each multiplexer.

Claim 23

A switch according to claim 11, including separate clock signals for each group of a selected number of groups of said multiplexer logic units.

Claim 24

A switch according to claim 11, including three state buffers on the output of each of said data output controllers and on the output from each of said control input/output units.

Claim 25

A digital crossbar switch for switching data between an internal data bus and one or more input/output data buses, comprising: plurality of multiplexer logic units: an m-bit internal data bus coupled to each of said multiplexer logic units where m is an integer; a plurality of n-bit input/output data buses one connected to each of said multiplexer logic units where n is an integer; a m/n to 1 channel selector, where m/n is an integer, in each multiplexer logic unit having an input connected to said internal data bus and an output coupled to a corresponding one of said input/output data buses and operative in response to a configuration control signal to switch a selected channel of data from said internal data bus to the corresponding input/output data bus; memory storage for configuration control signals coupled to said m/n to 1 multiplexer; and an input selector having an input coupled to a corresponding one of said input/output data buses and an output coupled to said internal data bus for transmitting a channel of data from said input/output data bus to said internal data bus in response to an input selector control signal.

Claim 26

A digital crossbar switch for switching data between an internal data bus and one or more input/output data buses, comprising: plurality of multiplexer logic units: an m-bit internal data bus coupled to each of said multiplexer logic units where m is an integer; a plurality of n-bit input/output data buses one connected to each of said multiplexer logic units where n is an integer; a m/n to 1 channel selector, where m/n is an integer, in each multiplexer logic unit having an input connected to said internal data bus and an output coupled to a corresponding one of said input/output data buses and operative in response to a configuration control signal to switch a selected channel of data from said internal data bus to the corresponding input/output data bus; memory storage for configuration control signals coupled to said m/n to 1 multiplexer; and an input selector having an input coupled to a corresponding one of said input/output data buses and an output coupled to said internal data bus for transmitting a channel of data from said input/output data bus to said internal data bus in response to an input selector control signal.

Claim 27

A switch according to claim 23, wherein data channels of said internal data bus are coupled to said multiplexer logic units so that data can be sent from a given multiplexer logic unit to one or more other multiplexer logic units along alternative multiple data paths in response to channel selector and input selector control signals.