EPROM device using asymmetrical transistor characteristics

Claim 2

An asymmetrical erasable programmable read only memory (EPROM) cell comprising: a semiconductor substrate having a surface; a source/drain region and a drain/source region in the semiconductor substrate spaced apart from each other by a channel between their inner edges; a gate dielectric material on the surface of the semiconductor substrate; a floating gate of conductive material on the gate dielectric material over the channel, and positioned such that the floating gate overlaps the inner edge of the drain/source region and is spaced apart from the inner edge of the source/drain region; a control gate of a conductive material positioned over and insulated from the floating gate; means for grounding the source/drain region and raising the drain/source and control gate to a positive potential during a write operation; and means for grounding the drain/source and ramping the voltage on the control gate during a read operation.

Claim 3

The EPROM cell of claim 1 wherein the semiconductor substrate is monocrystalline silicon, and the conductive material of the floating gate and the control gate is doped polycrystalline silicon.

Claim 4

The EPROM cell of claim 1 wherein a sidewall spacer exists on the thin dielectric layer between the floating gate and the source/drain region.

Claim 5

An asymmetrical erasable programmable read only memory (EPROM) cell comprising: a semiconductor substrate doped with an impurity of a first conductivity type and having a surface; a source/drain region and a drain/source region in the semiconductor substrate, where the source/drain region and the drain/source region are doped with an impurity of a second (semiconductor) conductivity type, and are spaced apart from each other by a channel between their inner edges; a gate dielectric material on the surface of the semiconductor substrate covering the channel; a floating gate of conductive material on the gate dielectric material over the channel, and positioned such that the floating gate overlaps the inner edge of the drain/source region and is spaced apart from the inner edge of the source/drain region; a control gate of a conductive material positioned over and insulated from the floating gate; means for grounding the source/drain region and raising the drain/source and control gate to a positive potential during a write operation; and means for grounding the drain/source and ramping the voltage on the control gate during a read operation.

Claim 6

An asymmetrical erasable programmable read only memory (EPROM) cell comprising: a semiconductor substrate doped with an impurity of a first conductivity type and having a surface; a source/drain region and a drain/source region in the semiconductor substrate, where the source/drain region and the drain/source region are doped with an impurity of a second (semiconductor) conductivity type, and are spaced apart from each other by a channel between their inner edges; a gate dielectric material on the surface of the semiconductor substrate covering the channel; a floating gate of conductive material on the gate dielectric material over the channel, and positioned such that the floating gate overlaps the inner edge of the drain/source region and is spaced apart from the inner edge of the source/drain region; a control gate of a conductive material positioned over and insulated from the floating gate; means for grounding the source/drain region and raising the drain/source and control gate to a positive potential during a write operation; and means for grounding the drain/source and ramping the voltage on the control gate during a read operation.

Claim 7

The EPROM cell of claim 4 wherein the semiconductor substrate is monocrystalline silicon, and the conductive material of the floating gate and the control gate is doped polycrystalline silicon.

Claim 8

The EPROM cell of claim 4 wherein a sidewall spacer exists on the thin dielectric layer between the floating gate and the source/drain region.

Claim 9

A process for producing an asymmetrical erasable programmable read only memory (EPROM) cell comprising the steps of: providing a semiconductor substrate; providing a first dielectric layer over the semiconductor substrate; providing a floating gate of conductive material on the dielectric layer; providing a second dielectric layer over the floating gate; providing a control gate of conductive material over the floating gate and the second dielectric layer; providing an asymmetrical non-charge storing spacer having a greater width on a first side of the floating and control gates than on the second side of said gates being the opposite side; and providing a source/drain region in the substrate on the first side of the gates spaced apart from the gates from the gates by portion of the asymmetrical non-charge storing having a greater width, and providing a drain/source region in the substrate on the second side of the gates, overlapped by the gates.

Claim 10

A process for producing an asymmetrical erasable programmable read only memory (EPROM) cell comprising the steps of: providing a semiconductor substrate; providing a first dielectric layer over the semiconductor substrate; providing a floating gate of conductive material on the dielectric layer; providing a second dielectric layer over the floating gate; providing a control gate of conductive material over the floating gate and the second dielectric layer; providing an asymmetrical non-charge storing spacer having a greater width on a first side of the floating and control gates than on the second side of said gates being the opposite side; and providing a source/drain region in the substrate on the first side of the gates spaced apart from the gates from the gates by portion of the asymmetrical non-charge storing having a greater width, and providing a drain/source region in the substrate on the second side of the gates, overlapped by the gates.

Claim 11

The process of claim 7 wherein the non-charge storing spacer is of the material selected from the group consisting of silicon dioxide, silicon nitride and combinations thereof.

Claim 12

A process for producing an asymmetrical erasable programmable read only memory (EPROM) cell comprising the steps of: providing a semiconductor substrate doped with an impurity of a first conductivity type; forming a first dielectric layer over the semiconductor substrate; forming and patterning a floating gate of conductive material on the dielectric layer, a second dielectric layer over the conductive material for the floating gate, and a control gate of conductive material over the conductive material for the floating gate and the second dielectric layer; providing a dielectric spacer selectively on a first side of the floating and control gates, the second side of said gates being the opposite side; introducing a source/drain region in the substrate on the first side of the gates and spaced apart from the gates, and introducing a drain/source region in the substrate on the second side of the gates, where the drain/source region is overlapped by the gates and where the source/drain region and the drain/source region are of the second conductivity type; and providing means to ground the source/drain region to perform as the source during a write operation and means to ground the drain/source region to perform as the source during a read operation.

Claim 13

A process for producing an asymmetrical erasable programmable read only memory (EPROM) cell comprising the steps of: providing a semiconductor substrate doped with an impurity of a first conductivity type; forming a first dielectric layer over the semiconductor substrate; forming and patterning a floating gate of conductive material on the dielectric layer, a second dielectric layer over the conductive material for the floating gate, and a control gate of conductive material over the conductive material for the floating gate and the second dielectric layer; providing a dielectric spacer selectively on a first side of the floating and control gates, the second side of said gates being the opposite side; introducing a source/drain region in the substrate on the first side of the gates and spaced apart from the gates, and introducing a drain/source region in the substrate on the second side of the gates, where the drain/source region is overlapped by the gates and where the source/drain region and the drain/source region are of the second conductivity type; and providing means to ground the source/drain region to perform as the source during a write operation and means to ground the drain/source region to perform as the source during a read operation.

Claim 14

The process of claim 9 wherein the first dielectric layer, second dielectric layer and dielectric spacer are of materials selected from the group of dielectric materials consisting of silicon dioxide, silicon nitride, combinations of the two.

Claim 15

The process of claim 9 wherein the semiconductor substrate is monocrystalline silicon.

Claim 16

The process of claim 9 wherein the conductive material of the floating gate and the control gate is doped polycrystalline silicon.

Claim 17

A process for producing an asymmetrical erasable programmable read only memory (EPROM) cell comprising the steps of: providing a semiconductor substrate doped with an impurity of a first conductivity type; forming a first dielectric layer over the semiconductor substrate; forming and patterning a floating gate of conductive material on the dielectric layer, a second dielectric layer over the conductive material for the floating gate, and a control gate of conductive material over the conductive material for the floating gate and the second dielectric layer; providing dielectric spacers around the gates; selectively removing a portion of the spacers, leaving the spacer on a first side of the floating and control gates, the second side of said gates without the spacer being the opposite side; introducing a source/drain region in the substrate on the first side of the gates and spaced apart from the gates, and introducing a drain/source region in the substrate on the second side of the gates, where the drain/source region is overlapped by the gates and where the source/drain region and the drain/source region are of the second conductivity type; and providing means to ground the source/drain region to perform as the source during a write operation and means to ground the drain/source region to perform as the source during a read operation.

Claim 18

A process for producing an asymmetrical erasable programmable read only memory (EPROM) cell comprising the steps of: providing a semiconductor substrate doped with an impurity of a first conductivity type; forming a first dielectric layer over the semiconductor substrate; forming and patterning a floating gate of conductive material on the dielectric layer, a second dielectric layer over the conductive material for the floating gate, and a control gate of conductive material over the conductive material for the floating gate and the second dielectric layer; providing dielectric spacers around the gates; selectively removing a portion of the spacers, leaving the spacer on a first side of the floating and control gates, the second side of said gates without the spacer being the opposite side; introducing a source/drain region in the substrate on the first side of the gates and spaced apart from the gates, and introducing a drain/source region in the substrate on the second side of the gates, where the drain/source region is overlapped by the gates and where the source/drain region and the drain/source region are of the second conductivity type; and providing means to ground the source/drain region to perform as the source during a write operation and means to ground the drain/source region to perform as the source during a read operation.

Claim 19

A process for producing an asymmetrical erasable programmable read only memory (EPROM) cell comprising the steps of: providing a semiconductor substrate doped with an impurity of a first conductivity type; forming a first dielectric layer over the semiconductor substrate; forming and patterning floating gate of conductive material on the dielectric layer, a second dielectric layer over the conductive material for the floating gate, and a control gate of conductive material over the conductive material for the floating gate and the second dielectric layer; introducing an impurity in the substrate on only a second side of the floating and control gates, an opposite side of the floating and control gates being the first side; providing a dielectric spacer around all sides of the floating and control gates; introducing a source/drain region in the substrate on the first side of the gates and spaced apart from the gates, and introducing a drain/source region in the substrate on the second side of the gates, where the drain/source region is overlapped by the gates and where the source/drain region and the drain/source region are of the second conductivity type; and providing means to enable the source/drain region to perform as the source during a write operation and means to enable the drain/source region to perform as the source during a read operation.

Claim 20

A process for producing an asymmetrical erasable programmable read only memory (EPROM) cell comprising the steps of: providing a semiconductor substrate doped with an impurity of a first conductivity type; forming a first dielectric layer over the semiconductor substrate; forming and patterning floating gate of conductive material on the dielectric layer, a second dielectric layer over the conductive material for the floating gate, and a control gate of conductive material over the conductive material for the floating gate and the second dielectric layer; introducing an impurity in the substrate on only a second side of the floating and control gates, an opposite side of the floating and control gates being the first side; providing a dielectric spacer around all sides of the floating and control gates; introducing a source/drain region in the substrate on the first side of the gates and spaced apart from the gates, and introducing a drain/source region in the substrate on the second side of the gates, where the drain/source region is overlapped by the gates and where the source/drain region and the drain/source region are of the second conductivity type; and providing means to enable the source/drain region to perform as the source during a write operation and means to enable the drain/source region to perform as the source during a read operation.