Fabricating process for large array semiconductive devices

Claim 1

A method of fabricating high resolution, large array semiconductive devices from the linear abutment of sub-units, each subunit having a planar semiconductive substrate with at least one component and supporting circuitry on a surface thereof and being obtained by the dicing of a semiconductive wafer containing of a surface thereof horizontal rows and vertical columns of said components with supporting circuit, said dicing being conducted along mutually perpendicular dicing lines between the rows and columns of components, so that said sub-units have precision surface edges to enable the sub-units to be abuttingly assembled with other sub-units to form a pagewidth array without loss of tolerance or resolution between adjacent sub-units in the large array, comprising the steps of: (a) sectioning the semiconductive wafer along parallel cutting lines between each two columns and one of the outermost columns of components and supporting circuitry formed on one of the surfaces thereof with a circular dicing blade, after adjusting the relative angular position of the dicing blade with respect to the wafer surface containing the components, so that the dicing blade produces a first slanted kerf through the semiconductive wafer along each cutting line, each of the first kerfs being slightly inwardly slanted at a predetermined angle θ and located closely adjacent one column of components and spaced from the other column of components when cutting is between columns; (b) turning the semiconductive wafer 180° and repeating step (a) along a parallel, separate cutting lines between the same columns and the other outermost column of components to produce a second kerf with the dicing blade at the same predetermined angular position, but with the opposite orientation, and located closely adjacent the columns of components that are further in distant from the first kerf, so that each column of components have inwardly directed kerfs on each side thereof; (c) dicing along parallel cutting lines between each row of components and supporting circuitry with the dicing blade generally normal to the semiconductive wafer and in a direction perpendicular to the first and second kerfs to produce a plurality of individual sub-units; and (d) fixedly abutting the sub-units with their confronting edges being produced by the inwardly slanted kerfs, so that they are in precise linear contact at the surface of the sub-units' planar substrate containing the components, while the opposite surfaces of sub-units' planar substrates are spaced apart.

Claim 2

A method of fabricating high resolution, large array semiconductive devices from the linear abutment of sub-units, each subunit having a planar semiconductive substrate with at least one component and supporting circuitry on a surface thereof and being obtained by the dicing of a semiconductive wafer containing of a surface thereof horizontal rows and vertical columns of said components with supporting circuit, said dicing being conducted along mutually perpendicular dicing lines between the rows and columns of components, so that said sub-units have precision surface edges to enable the sub-units to be abuttingly assembled with other sub-units to form a pagewidth array without loss of tolerance or resolution between adjacent sub-units in the large array, comprising the steps of: (a) sectioning the semiconductive wafer along parallel cutting lines between each two columns and one of the outermost columns of components and supporting circuitry formed on one of the surfaces thereof with a circular dicing blade, after adjusting the relative angular position of the dicing blade with respect to the wafer surface containing the components, so that the dicing blade produces a first slanted kerf through the semiconductive wafer along each cutting line, each of the first kerfs being slightly inwardly slanted at a predetermined angle θ and located closely adjacent one column of components and spaced from the other column of components when cutting is between columns; (b) turning the semiconductive wafer 180° and repeating step (a) along a parallel, separate cutting lines between the same columns and the other outermost column of components to produce a second kerf with the dicing blade at the same predetermined angular position, but with the opposite orientation, and located closely adjacent the columns of components that are further in distant from the first kerf, so that each column of components have inwardly directed kerfs on each side thereof; (c) dicing along parallel cutting lines between each row of components and supporting circuitry with the dicing blade generally normal to the semiconductive wafer and in a direction perpendicular to the first and second kerfs to produce a plurality of individual sub-units; and (d) fixedly abutting the sub-units with their confronting edges being produced by the inwardly slanted kerfs, so that they are in precise linear contact at the surface of the sub-units' planar substrate containing the components, while the opposite surfaces of sub-units' planar substrates are spaced apart.

Claim 3

The method of claim1, wherein the sub-units are image sensors and the components are linear arrays of photosites; and wherein the semiconductive wafer and thus the planar semiconductive substrate is silicon or gallium arsenide.