Logic circuit using resonant-tunneling transistor

Claim 2

A logic circuit comprising: a resonant-tunneling transistor including a superlattice containing at least one quantum well layer; and means serially connected to a junction between a base and an emitter of said transistor and supplying a constant current to said base; said transistor having a differential negative-resistance characteristic with at least one resonant point in a relationship between a current flowing through said base and a voltage between said base and emitter, and having at least two stable base current values at both sides of said resonant point on said characteristic, defined by said changeable base emitter voltage.

Claim 3

A logic circuit according to claim 1, further comprising load means operatively connected to a collector of said transistor, and output means operatively connected to a commonly connected point of said load means and said collector, for outputting a voltage defined by a change of a current flowing through said collector, which voltage is varied in response to said two stable base current values.

Claim 4

A logic circuit according to claim 2, wherein said resonant-tunneling transistor comprises a resonant-tunneling hot electron transistor.

Claim 5

A logic circuit according to claim 2, wherein said resonant-tunneling transistor comprises a resonant-tunneling bipolar transistor.

Claim 6

A logic circuit comprising: a resonant-tunneling transistor having a superlattice containing at least one quantum well layer; means serially connected to a junction between a base and an emitter of said transistor for supplying a constant current to said base; and write means operatively connected to a collector of said transistor for changing a voltage at said collector, said transistor having a differential negative-resistance characteristic having at least one resonant point of a resonant-tunneling effect in a relationship between a current flowing through said base and a voltage between said base and emitter, and having at least two stable base current values at both sides of said resonant point, defined by said base.emitter voltage, said write means changing the collector voltage to change a current flowing through said collector and said base.emitter voltage being changed in response to the change of said collector voltage, so that said transistor holds one of at least two stable states defined by said stable base current values in response to said change of said collector voltage.

Claim 7

A logic circuit comprising: a resonant-tunneling transistor having a superlattice containing at least one quantum well layer; means serially connected to a junction between a base and an emitter of said transistor for supplying a constant current to said base; and write means operatively connected to a collector of said transistor for changing a voltage at said collector, said transistor having a differential negative-resistance characteristic having at least one resonant point of a resonant-tunneling effect in a relationship between a current flowing through said base and a voltage between said base and emitter, and having at least two stable base current values at both sides of said resonant point, defined by said base.emitter voltage, said write means changing the collector voltage to change a current flowing through said collector and said base.emitter voltage being changed in response to the change of said collector voltage, so that said transistor holds one of at least two stable states defined by said stable base current values in response to said change of said collector voltage.

Claim 8

A logic circuit according to claim 5, wherein said resonant-tunneling transistor comprises a resonant-tunneling hot electron transistor.

Claim 9

A logic circuit according to claim 5, wherein said resonant-tunneling transistor comprises a resonant-tunneling bipolar transistor.

Claim 10

A semiconductor memory device comprising a plurality of memory cells arranged between a plurality of bit lines and a plurality of word lines in a matrix fashion, each memory cell including, an resonant-tunneling transistor having a superlattice containing at least one quantum well layer, means serially connected to a junction between a base and an emitter of said transistor for supplying a constant current to said base, means operatively connected to a collector of said transistor and supplying a current flowing through said collector via a resistor therein, and a switching means operatively connected between a commonly connected point of said collector and said resistor in said current supply means and a corresponding bit line and having a control terminal operatively connected to a corresponding word line, said transistor having a differential negative-resistance characteristic having at least one resonant point of a resonant-tunneling effect in a relationship between a current flowing through said base and a voltage between said base and emitter, and having at least two stable base current values at both sides of said resonant point, defined by said base.emitter voltage, said transistor holding one of at least two stable states in response to the change of a voltage at said collector supplied through said switching means in a combination of voltages on said bit line and said word line, and said transistor outputting one of at least two voltages corresponding to said held stable states to said bit line through said switching means energized by a voltage on said word line.

Claim 11

A semiconductor memory device comprising a plurality of memory cells arranged between a plurality of bit lines and a plurality of word lines in a matrix fashion, each memory cell including, an resonant-tunneling transistor having a superlattice containing at least one quantum well layer, means serially connected to a junction between a base and an emitter of said transistor for supplying a constant current to said base, means operatively connected to a collector of said transistor and supplying a current flowing through said collector via a resistor therein, and a switching means operatively connected between a commonly connected point of said collector and said resistor in said current supply means and a corresponding bit line and having a control terminal operatively connected to a corresponding word line, said transistor having a differential negative-resistance characteristic having at least one resonant point of a resonant-tunneling effect in a relationship between a current flowing through said base and a voltage between said base and emitter, and having at least two stable base current values at both sides of said resonant point, defined by said base.emitter voltage, said transistor holding one of at least two stable states in response to the change of a voltage at said collector supplied through said switching means in a combination of voltages on said bit line and said word line, and said transistor outputting one of at least two voltages corresponding to said held stable states to said bit line through said switching means energized by a voltage on said word line.

Claim 12

A semiconductor memory device according to claim 8, wherein said resonant-tunneling transistor comprises a resonant-tunneling hot electron transistor.

Claim 13

A semiconductor memory device according to claim 8, wherein said resonant-tunneling transistor comprises a resonant-tunneling bipolar transistor.

Claim 14

A latch circuit comprising: a resonant-tunneling transistor including a superlattice containing at least one quantum well layer; means serially connected to a junction between a base and an emitter of said transistor for supplying a constant current to said base; and write means operatively connected to said base and supplying a write voltage to said base; said transistor having a differential negative-resistance characteristic having at least one resonant point of a resonant-tunneling effect in a relationship between a current flowing through said base and a voltage between said base and emitter, and having at least two stable base current values at both sides of said resonant point, defined by said base.emitter voltage, said write means supplying one of at least two write voltages corresponding to said stable base current values to said base to change said base. emitter voltage so that the transistor holds one stable state defined by said changed base.emitter voltage.

Claim 15

A latch circuit comprising: a resonant-tunneling transistor including a superlattice containing at least one quantum well layer; means serially connected to a junction between a base and an emitter of said transistor for supplying a constant current to said base; and write means operatively connected to said base and supplying a write voltage to said base; said transistor having a differential negative-resistance characteristic having at least one resonant point of a resonant-tunneling effect in a relationship between a current flowing through said base and a voltage between said base and emitter, and having at least two stable base current values at both sides of said resonant point, defined by said base.emitter voltage, said write means supplying one of at least two write voltages corresponding to said stable base current values to said base to change said base. emitter voltage so that the transistor holds one stable state defined by said changed base.emitter voltage.

Claim 16

A latch circuit according to claim 11, wherein said latch circuit outputs a current at said collector which is changeable in response to said state held in said transistor.

Claim 17

A latch circuit according to claim 12, further comprising means connected to said collector and supplying a current to said collector through a resistor therein, wherein said latch circuit outputs a voltage at said collector in response to said state held in said transistor.

Claim 18

A latch circuit according to claim 11, further, comprising means connected to said collector and supplying a current to said collector through a resistor therein, wherein said latch circuit outputs a voltage at said collector in response to said state held in said, transistor.

Claim 19

A latch circuit according to claim 11, wherein said resonant-tunneling transistor comprises a resonant-tunneling hot electron transistor.

Claim 20

A latch circuit according to claim 11, wherein said resonant-tunneling transistor comprises a resonant-tunneling bipolar transistor.

Claim 21

A latch circuit comprising: a resonant-tunneling transistor including a superlattice containing at least one quantum well layer; means serially connected to a junction between a base and an emitter of said resonant-tunneling transistor for supplying a constant current to said base; and write means operatively connected to said base and supplying a write voltage to said base, said write means including: switching means having a first terminal operatively connected to said base, a second terminal for receiving a data signal and a control terminal for receiving a control signal for energizing said switching means, said switching means sending the data signal having one amplitude of at least two amplitudes corresponding to the stable base current values, to said base in response to the control signal for changing the base emitter voltage such that said transistor holds one stable state defined by the changed base emitter voltage; said transistor having a differential negative-resistance characteristic having at least one resonant point of a resonant-tunneling effect in a relationship between a current flowing through said base and a voltage between said base and emitter, and having at least two stable base current values at both sides of said resonant point defined by said base emitter voltage; and said write means supplying one of at least two write voltages corresponding to the stable base current values, to said base for changing the base emitter voltage such that said transistor holds one stable state defined by the changed base emitter voltage.

Claim 22

A latch circuit comprising: a resonant-tunneling transistor including a superlattice containing at least one quantum well layer; means serially connected to a junction between a base and an emitter of said resonant-tunneling transistor for supplying a constant current to said base; and write means operatively connected to said base and supplying a write voltage to said base, said write means including: switching means having a first terminal operatively connected to said base, a second terminal for receiving a data signal and a control terminal for receiving a control signal for energizing said switching means, said switching means sending the data signal having one amplitude of at least two amplitudes corresponding to the stable base current values, to said base in response to the control signal for changing the base emitter voltage such that said transistor holds one stable state defined by the changed base emitter voltage; said transistor having a differential negative-resistance characteristic having at least one resonant point of a resonant-tunneling effect in a relationship between a current flowing through said base and a voltage between said base and emitter, and having at least two stable base current values at both sides of said resonant point defined by said base emitter voltage; and said write means supplying one of at least two write voltages corresponding to the stable base current values, to said base for changing the base emitter voltage such that said transistor holds one stable state defined by the changed base emitter voltage.

Claim 23

A dynamic frequency divider comprising: a resonant-tunneling transistor including a superlattice containing at least one quantum well layer; means serially connected to a junction between a base and an emitter of said transistor for supplying a constant current to said base; means operatively connected to a collector and supplying a current flowing through said collector through a resistor therein; and signal input means operatively connected to said base and having a data input terminal and a clock input terminal; said data input terminal and said collector being connected, said transistor having a differential negative-resistance characteristic having at least one resonant point of a resonant-tunneling effect in a relationship between a current flowing through said base and a voltage between said base and emitter, and having at least two stable base current values at both sides of said resonant point, defined by said base.emitter voltage, an input signal having a predetermined frequency and an amplitude of at least two amplitudes corresponding to said stable base current values, being supplied to said clock input terminal so that an output signal of a half of said input frequency is output from said collector.

Claim 24

A dynamic frequency divider comprising: a resonant-tunneling transistor including a superlattice containing at least one quantum well layer; means serially connected to a junction between a base and an emitter of said transistor for supplying a constant current to said base; means operatively connected to a collector and supplying a current flowing through said collector through a resistor therein; and signal input means operatively connected to said base and having a data input terminal and a clock input terminal; said data input terminal and said collector being connected, said transistor having a differential negative-resistance characteristic having at least one resonant point of a resonant-tunneling effect in a relationship between a current flowing through said base and a voltage between said base and emitter, and having at least two stable base current values at both sides of said resonant point, defined by said base.emitter voltage, an input signal having a predetermined frequency and an amplitude of at least two amplitudes corresponding to said stable base current values, being supplied to said clock input terminal so that an output signal of a half of said input frequency is output from said collector.

Claim 25

A dynamic frequency divider according to claim 18, wherein said signal input means includes switching means having a terminal operatively connected to said base and another terminal as said data input terminal and a control terminal as said clock input terminal.

Claim 26

A dynamic frequency divider according to claim 18, wherein said resonant-tunneling transistor comprises a resonant-tunneling hot electron transistor.

Claim 27

A dynamic frequency divider according to claim 18, wherrein said resonant-tunneling transistor comprises a resonant-tunneling bipolar transistor.

Claim 28

A static frequency divider comprising: a first delay-type flip-lop (D-FF), having a clock input terminal receiving an input signal; a second D-FF having a data input terminal operatively connected to an positive output terminal of said first D-FF; a first inverter provided between said clock input terminal of said first D-FF and a clock input terminal of said second FF; and a second inverter operatively connecting a positive output terminal of said second FF and a data input terminal of said first D-FF; each D-FF including, a resonant-tunneling transistor including a superlattice containing at least one quantum well layer, means serially connected to a junction between a base and an emitter of said transistor for supplying a constant current to said base, means operatively connected to a collector and supplying a current flowing through said collector through a resistor therein, and signal input means operatively connected to said base and having a data input terminal and a clock input terminal, said transistor having a differential negative-resistance characteristic having at least one resonant point of a resonant-tunneling effect in a relationship between a current flowing through said base and a voltage between said base and emitter, and having at least two stable base current values at both sides of said resonant point, defined by said base.emitter voltage, an input signal having a predetermined frequency and an amplitude of at least two amplitudes corresponding to said stable base current values, being supplied to said clock input terminal of said first D-FF so that an output signal of a half of said input frequency is output from said positive output terminal of said second D-FF.

Claim 29

A static frequency divider comprising: a first delay-type flip-lop (D-FF), having a clock input terminal receiving an input signal; a second D-FF having a data input terminal operatively connected to an positive output terminal of said first D-FF; a first inverter provided between said clock input terminal of said first D-FF and a clock input terminal of said second FF; and a second inverter operatively connecting a positive output terminal of said second FF and a data input terminal of said first D-FF; each D-FF including, a resonant-tunneling transistor including a superlattice containing at least one quantum well layer, means serially connected to a junction between a base and an emitter of said transistor for supplying a constant current to said base, means operatively connected to a collector and supplying a current flowing through said collector through a resistor therein, and signal input means operatively connected to said base and having a data input terminal and a clock input terminal, said transistor having a differential negative-resistance characteristic having at least one resonant point of a resonant-tunneling effect in a relationship between a current flowing through said base and a voltage between said base and emitter, and having at least two stable base current values at both sides of said resonant point, defined by said base.emitter voltage, an input signal having a predetermined frequency and an amplitude of at least two amplitudes corresponding to said stable base current values, being supplied to said clock input terminal of said first D-FF so that an output signal of a half of said input frequency is output from said positive output terminal of said second D-FF.

Claim 30

A static frequency divider according to claim 22, wherein said signal input means includes a switching means having a terminal operatively connected to said base and another terminal as said data input terminal and a control terminal as said clock input terminal.

Claim 31

A static frequency divider according to claim 23, wherein said resonant-tunneling transistor comprises a resonant-tunneling hot electron transistor.

Claim 32

A static frequency divider according to claim 23, wherein said resonant-tunneling transistor comprises a resonant-tunneling bipolar transistor.