Duty cycle independent phase detector

Claim 2

A phase detecting circuit comprising: a first bistable circuit having a data input, a clock input, a reset input and a NOT Q output, wherein said first fistable circuit data input is connected to a predetermined logic signal and wherein said NOT Q output goes to a logic low state when a logic high signal is received at said first circuit clock input and said first circuit reset input is receiving a logic low signal, and said NOT Q output goes to a logic high state when a logic high signal is received at said first circuit reset input; a second bistable circuit having a data input, a clock input, a reset input, and a Q output, wherein said second circuit data input is connected to said predetermined logic signal and wherein said Q output goes to a logic high state when a logic high signal is received at said second circuit clock input and said second circuit reset input is receiving a logic low signal, and said Q output goes to a logic low state when a logic high signal is received at said second circuit reset input; said NOT Q output of said first bistable circuit being connected to said reset input of said second bistable circuit; said Q output of said second bistable circuit being connected to said reset input of said first bistable circuit; means for connecting the data inputs of said first and second bistable circuits to a logic signal having a predetermined logic state; means for connecting a reference data signal to the clock input of said first bistable circuit; means for connecting a second data signal to the clock input of said second bistable circuit; wherein the average value of the voltage appearing on the NOT Q output of said first bistable circuit is proportional to the phase difference between the reference data signal and the second data signal.

Claim 3

A phase detecting circuit as recited in claim 1, wherein said average value varies linearly from a first predetermined voltage level to a second predetermined voltage level as the phase difference between said reference signal and said controlled data signal varies from -180° to +180°.

Claim 4

A phase detecting circuit as recited in claim 1, wherein said means for connecting the second data signal to the clock input of the second bistable circuit, comprises: an inverter having an input for receiving said second data signal and having an output connected to the clock input of said second bistable circuit.

Claim 5

A phase detecting circuit as recited in claim 3, further comprising: a voltage dividing circuit branch connected between the NOT Q output of said first bistable circuit and the input of said inverter.

Claim 6

A phase detecting circuit as recited in claim 4, wherein said voltage dividing circuit branch comprises: a pair of resistors electrically connected in series, wherein the average voltage appearing at the junction of said resistors is proportional to the phase difference between said reference data signal and said second data signal.

Claim 7

A phase detecting circuit as recited in claim 1, wherein said first and second bistable circuits are type D flip-flop circuits.

Claim 8

A phase-locked loop circuit comprising: a first bistable circuit having a data input, a clock input, a reset input and a NOT Q output, wherein said first circuit data input is connected to a predetermined logic signal and wherein said NOT Q output goes to a logic low state when a logic high signal is received at said first circuit clock input and said first circuit reset input is receiving a logic low signal, and said NOT Q output goes to a logic high state when a logic high signal is received at said first circuit reset input; a second bistable circuit having a data input, a clock input, a reset input, and a Q output, wherein said second circuit data input is connected to said predetermined logic signal and wherein said Q output goes to a logic high state when a logic high signal is received at said second circuit clock input and said second circuit reset input is receiving a logic low signal, and said Q output goes to a logic low state when a logic high signal is received at said second circuit reset input; said NOT Q output of said first bistable circuit being connected to said reset input of said second bistable circuit; said Q output of said second bistable circuit being connected to said reset input of said first bistable circuit; means for connecting a reference data signal to the clock input of said first bistable circuit; an inverter having an input for receiving a second data signal and having an output connected to the clock input of said second bistable circuit; a voltage dividing circuit branch connected between the NOT Q output of said first bistable circuit and the input of said inverter; wherein the average value of the voltage appearing at an intermediate point in said voltage dividing circuit is proportional to the phase difference between the reference data signal and the second data signal; means for shifting the magnitude of said average voltage by a fixed amount; means for integrating the shifted magnitude average voltage to obtain a frequency control signal; and means for generating said second data signal in response to said frequency control signal

Claim 9

A phase-locked loop circuit comprising: a first bistable circuit having a data input, a clock input, a reset input and a NOT Q output, wherein said first circuit data input is connected to a predetermined logic signal and wherein said NOT Q output goes to a logic low state when a logic high signal is received at said first circuit clock input and said first circuit reset input is receiving a logic low signal, and said NOT Q output goes to a logic high state when a logic high signal is received at said first circuit reset input; a second bistable circuit having a data input, a clock input, a reset input, and a Q output, wherein said second circuit data input is connected to said predetermined logic signal and wherein said Q output goes to a logic high state when a logic high signal is received at said second circuit clock input and said second circuit reset input is receiving a logic low signal, and said Q output goes to a logic low state when a logic high signal is received at said second circuit reset input; said NOT Q output of said first bistable circuit being connected to said reset input of said second bistable circuit; said Q output of said second bistable circuit being connected to said reset input of said first bistable circuit; means for connecting a reference data signal to the clock input of said first bistable circuit; an inverter having an input for receiving a second data signal and having an output connected to the clock input of said second bistable circuit; a voltage dividing circuit branch connected between the NOT Q output of said first bistable circuit and the input of said inverter; wherein the average value of the voltage appearing at an intermediate point in said voltage dividing circuit is proportional to the phase difference between the reference data signal and the second data signal; means for shifting the magnitude of said average voltage by a fixed amount; means for integrating the shifted magnitude average voltage to obtain a frequency control signal; and means for generating said second data signal in response to said frequency control signal

Claim 10

A phase-locked loop circuit as recited in claim 7, wherein said voltage divider circuit branch comprises: a pair of resistors electrically connected in series, and wherein said intermediate point is the common connection of said resistors.

Claim 11

A phase-locked loop circuit as recited in claim 7, wherein said means for shifting the magnitude of said average voltage comprises: a summing means which adds a fixed voltage to said average voltage.