US4843256A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Controlled CMOS substrate voltage generator
Assignee: Jenoptik AG
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Filing: 1987-11-13
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Granted: 1989-06-27
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Expires: 2007-11-13
Abstract
Abstract A controlled CMOS substrate voltage generator generates a rectangular wave pulse which is supplied to the pumping circuit by a pumping capacitor and controlled decoupling members. At the same time the decoupling members are activated by a control circuit and are completely opened, so that the full pumping lift is completely utilized without reduction due to threshold voltages. In order to reduce the injection of charge carriers of nCMOS decoupling members, inversely activated pMOS decoupling members, which are strongly conducting at low substrate bias voltage near 0V, are connected in parallel to the latter. To increase performance, the circuit is designed as a circuit in phase opposition. Improved sensors are provided, which during the active phase maintain the shift of the substrate voltage produced upon wobble of the bit strings toward more negative values by alternation of the reference voltage of the sensor.
Inventors
- 👤 Andreas Scade
- 👤 Reinhard Hoenig
- 👤 Horst-Guenther Schniek
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 14:05
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/211; H10D89/213; H10D89/215; G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/205
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
340 words
In a controlled CMOS substrate voltage generator having a comparator for comparing a substrate voltage and ground potential, a ring oscillator coupled to the output of the comparator, an amplifier coupled to the output of the oscillator, a pumping circuit coupled to the output of the amplifier, the comparator being comprised of a sensor with an amplifier, the sensor being comprised of a series arrangement of a power source and a resistance combination connected between the supply voltage and the substrate, the resistance combination being comprised of MOS transistors, the supply voltage comprising an essentially constant output voltage across the resistance combination with respect to ground, the improvement comprising first delay means and second inverting delay means, the pumping circuit comprising first and second pumping circuits each having a pumping capacitor and parallel connected nMOS and pMOS decoupling means connected between the respective pumping capacitor and signal ground, said decoupling means having gates, said first and second pumping circuits also having separate pMOS diodes, the output of the amplifier being connected to the first pumping circuit via the first delay means and to the second pumping circuit via the second inverting delay means whereby the first and second pumping circuits operate in phase opposition, the first and second delay means having the same time lag (π 1 ), a first control circuit comprised of a third inverting delay means and a first capacitor connected between the amplifier and the gates of the decoupling members of the first pumping circuit, and a second control circuit comprised of a fourth delay means and a second capacitor connected between the amplifier and the gates of the decoupling means of the second pumping circuit, the third and fourth delay means having the same time lag (π 2 ), which is smaller than the time lag (π 1 ), the gates of the decoupling means of the first and second pumping circuits being connected to the respective pMOS diodes, said diodes being biased in the direction of flow and having ground potential (U SS ).
Claim 2
Dependent Claim
340 words
In a controlled CMOS substrate voltage generator having a comparator for comparing a substrate voltage and ground potential, a ring oscillator coupled to the output of the comparator, an amplifier coupled to the output of the oscillator, a pumping circuit coupled to the output of the amplifier, the comparator being comprised of a sensor with an amplifier, the sensor being comprised of a series arrangement of a power source and a resistance combination connected between the supply voltage and the substrate, the resistance combination being comprised of MOS transistors, the supply voltage comprising an essentially constant output voltage across the resistance combination with respect to ground, the improvement comprising first delay means and second inverting delay means, the pumping circuit comprising first and second pumping circuits each having a pumping capacitor and parallel connected nMOS and pMOS decoupling means connected between the respective pumping capacitor and signal ground, said decoupling means having gates, said first and second pumping circuits also having separate pMOS diodes, the output of the amplifier being connected to the first pumping circuit via the first delay means and to the second pumping circuit via the second inverting delay means whereby the first and second pumping circuits operate in phase opposition, the first and second delay means having the same time lag (π 1 ), a first control circuit comprised of a third inverting delay means and a first capacitor connected between the amplifier and the gates of the decoupling members of the first pumping circuit, and a second control circuit comprised of a fourth delay means and a second capacitor connected between the amplifier and the gates of the decoupling means of the second pumping circuit, the third and fourth delay means having the same time lag (π 2 ), which is smaller than the time lag (π 1 ), the gates of the decoupling means of the first and second pumping circuits being connected to the respective pMOS diodes, said diodes being biased in the direction of flow and having ground potential (U SS ).
Claim 3
Dependent Claim
96 words
Controlled CMOS substrate voltage generator according to claim 1, further comprising first and second pMOS decoupling means having gates and being connected in parallel with the nMOS decoupling means of the first and second pumping circuits respectively, the gates of the first and second pMOS decoupling means being connected to the second and first control circuits, respectively, and further comprising first and second pMOS discharge transistors arranged between the gates of the first and second pMOS decoupling members respectively and ground (U SS ) and having gates controlled by the first and second control circuits, respectively.
Claim 4
Dependent Claim
18 words
Controlled CMOS substrate voltage generator according to claim 1, wherein said ring oscillator has a constant transient response.
Claim 5
Dependent Claim
55 words
Controlled CMOS substrate voltage generator according to claim 1, wherein the sensor comprises a series circuit of first and second MOS transistors, and further comprising a third MOS transistor connected in parallel with the second MOS transistor, and further comprising an external terminal, said third MOS transistor having a gate connected to said external terminal.
Claim 6
Dependent Claim
30 words
Controlled CMOS substrate voltage generator according to claim 4, wherein the line selection signal (e,ovs/RAS/ ) is connected to the gate of said third MOS transistor by a threshold switch.
Claim 7
Dependent Claim
30 words
Controlled CMOS substrate voltage generator according to claim 4, wherein a source of a line selection signal (RAS) is connected by way of a threshold switch to said external terminal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-26 | 1992-12-26 | 1993-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-26 | 1996-12-26 | 1997-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-26 | 2000-12-26 | 2001-06-27 | $7700.00 | Window Closed / Lapsed |