Read/write memory device with an embedded read-only pattern and method for providing same

Claim 2

A memory array device with an embedded binary pattern, said memory array device comprising: a first voltage line and a second voltage line; an array of bistable memory cell means, each of said bistable memory cell means being associated with a respective address value and being constructed with first and second sides that each are selectively connectable to said first voltage line or said second voltage line, each of said bistable memory cell means, when said first and second sides are selectively connected to opposite ones of said first and second voltage line, being for: (a) functioning, during times when said first and second voltage lines are energized at a same time and voltage level, in a bistable mode; and (b) functioning, during times when said first and second voltage lines are energized at at least one of different times and different voltage levels, in an embedded binary pattern mode wherein each of said bistable memory cell means being set to a logical value corresponding to a selected connection of said first and second sides of said bistable memory cell means to said first and second voltage lines.

Claim 3

A memory array device with an embedded binary pattern said memory array device comprising: a first voltage line and a second voltage line; an array of bistable memory cell means are different groups of said bistable memory cell means are associated with respective address values and each of said bistable memory cell means being constructed with first and second sides that are each selectively connectable to said first voltage line or said second voltage line, each of said bistable memory cell means, when said first and second sides are selectively connected to opposite ones of said first and second voltage line, being for: (a) functioning, during times when said first and second voltage lines are energized at a same time and voltage level, in a bistable mode; and (b) functioning, during times when said first and second voltage lines are energized at at least one of different times and different voltage levels, in an embedded binary pattern mode wherein each of said bistable memory cell means is set to a logical value corresponding to the selected connection of said first and second sides of said bistable memory cell means to said first and second voltage lines.

Claim 4

A memory array device with an embedded binary pattern said memory array device comprising: a first voltage line and a second voltage line; an array of bistable memory cell means are different groups of said bistable memory cell means are associated with respective address values and each of said bistable memory cell means being constructed with first and second sides that are each selectively connectable to said first voltage line or said second voltage line, each of said bistable memory cell means, when said first and second sides are selectively connected to opposite ones of said first and second voltage line, being for: (a) functioning, during times when said first and second voltage lines are energized at a same time and voltage level, in a bistable mode; and (b) functioning, during times when said first and second voltage lines are energized at at least one of different times and different voltage levels, in an embedded binary pattern mode wherein each of said bistable memory cell means is set to a logical value corresponding to the selected connection of said first and second sides of said bistable memory cell means to said first and second voltage lines.

Claim 5

A memory array device as claimed in claim 2, wherein said embedded binary pattern corresponds to an instruction set, and wherein logical values of each of said different group of bistable memory cell means represents an instruction in said instruction set.

Claim 6

A memory array device as claimed in claim 2, wherein said embedded binary pattern corresponds to a self-test signature pattern and wherein logical values of each said different group of bistable memory cell means represents a different signature portion of said self-test signature pattern.

Claim 7

A memory array device as claimed in claim 2, wherien said embedded binary pattern corresponds to a self-test binary count sequence, and wherein logical values of each said different group of bistable memory cell means represents a binary count value.

Claim 8

A memory array device as claimed in claim 5, further comprising feedback loop means for applying said binary count values as address values to cause said memory array to progress through said self-test binary count sequence during a self-test operation.

Claim 9

A memory array device as claimed in claim 6, wherein said feedback loop means comprises delay means for introducing a delay in the application of said binary count values as address values so that a race condition does not occur.

Claim 10

A memory array device as claimed in claim 7, wherein said feedback loop means comprises latch means, responsive to a clock pulse, for controlling the rate at which said binary count values are applied as address values.

Claim 11

A memory array device as claimed in claim 7, further comprising recording means for recording logical values of each of said different groups of bistable memory cell means as said memory array device progresses through a self-test operation.

Claim 12

A memory array device as claimed in claim 9, wherein said recording means comprises memory means for recording logical values upon receipt of a clock pulse and wherein said memory array device further comprises clock generation means for producing a clock pulse in synchronization with a sequencing of said memory array through a self-test operation.

Claim 13

A memory array device as claimed in claim 7, further comprising cycle means for halting a self-test operation once said memory array has completed an entire self-test cycle.

Claim 14

A memory array device with an embedded binary pattern, said memory array device comprising: a first voltage line and a second voltage line; an array of bistable memory cell means, each of said bistable memory cell means being associated with a respective address value and each of said bistable memory cell means being constructed with first and second sides, said first side being selectively connected to one of said first voltage line or said second voltage line and said second side being selectively connected to one of said first voltage line or said second voltage line which is not connected to said first side of said bistable memory cell means, each of said bistable memory cell means being for: (a) functioning, during times when said first and second voltage lines are energized at a same time and voltage level, in a bistable mode; and (b) functioning, during times when said first and second voltage lines are energized at at least one of different times and different voltage levels, in an embedded binary pattern mode wherein each of said bistable memory cell means is set to a logical value corresponding to a selected connection of said first and second sides of said bistable memory cell means to said first and second voltage lines.

Claim 15

A memory array device with an embedded binary pattern, said memory array device comprising: a first voltage line and a second voltage line; an array of bistable memory cell means, each of said bistable memory cell means being associated with a respective address value and each of said bistable memory cell means being constructed with first and second sides, said first side being selectively connected to one of said first voltage line or said second voltage line and said second side being selectively connected to one of said first voltage line or said second voltage line which is not connected to said first side of said bistable memory cell means, each of said bistable memory cell means being for: (a) functioning, during times when said first and second voltage lines are energized at a same time and voltage level, in a bistable mode; and (b) functioning, during times when said first and second voltage lines are energized at at least one of different times and different voltage levels, in an embedded binary pattern mode wherein each of said bistable memory cell means is set to a logical value corresponding to a selected connection of said first and second sides of said bistable memory cell means to said first and second voltage lines.

Claim 16

A memory array device as claimed in claim 12, wherein said embedded binary pattern is an embedded self-test pattern which corresponds to a binary count sequence and wherein logical values of each different group of bistable memory cell means represents a binary count value.

Claim 17

A memory array device as claimed in claim 13, further comprising feedback loop means for applying said binary count values as address values to cause said memory array to progress through said binary count sequence during a self-test operation.

Claim 18

A memory array device as claimed in claim 14, wherein said feedback loop means comprises delay means for introducing a delay in the application of said binary count values as address values so that a race condition does not occur.

Claim 19

A memory array device as claimed in claim 15, wherein said feedback loop means comprises latch means responsive to a clock pulse, for controlling a rate at which binary count values are applied as address values.

Claim 20

A memory array device as claimed in claim 15, further comprising recording means for recording logical values of each different group of bistable memory cell means as said memory array device progresses through a self-test operation.

Claim 21

A memory array device as claimed in claim 17, wherein said recording means comprises memory means for recording logical values upon receipt of a clock pulse, and wherein said memory array device further comprises clock generation means for producing a clock pulse in synchronization with a sequencing of said memory array through a self-test operation.

Claim 22

A memory array device as claimed in claim 15, further comprising cycle means for halting a self-test operation once said memory array has completed an entire self-test cycle.

Claim 23

A memory array device with an embedded binary pattern and a complementary embedded binary pattern, said memory array device comprising: a first voltage line and a second voltage line; an array of bistable memory cell means, each of said bistable memory cell means being associated with a respective address value and each of said bistable cells being constructed with first and second sides, said first side being selectively connected to one of said first voltage line or said second voltage line and said second side being selectively connected to one of said first voltage line or said second voltage line which is not connected to said first side of said bistable memory cell means, each of said bistable memory cell means being for: (a) functioning, during times when said first and second voltage lines are energized at a same time and voltage level, in a read/write mode, wherein said bistable memory cell means can be set to either a logical 1 or 0; (b) functioning, during times when said first voltage line is energized at at least one of an earlier time or a higher voltage level than an energization of said second voltage line, in an embedded binary pattern mode wherein each of said bistable memory cell means is set to a logical value corresponding to a selected connection of said first and second sides of said bistable memory cell means to said first or second voltage lines; and (c) functioning, during times when said second voltage line is energized at at least one of an earlier time or a higher voltage level than an energization level of said first voltage line, in a complementary embedded binary pattern mode wherein each of said bistable memory cell means is set to a logical value which is a complement of a logical value which would be obtained from function (b) above.

Claim 24

A memory array device with an embedded binary pattern and a complementary embedded binary pattern, said memory array device comprising: a first voltage line and a second voltage line; an array of bistable memory cell means, each of said bistable memory cell means being associated with a respective address value and each of said bistable cells being constructed with first and second sides, said first side being selectively connected to one of said first voltage line or said second voltage line and said second side being selectively connected to one of said first voltage line or said second voltage line which is not connected to said first side of said bistable memory cell means, each of said bistable memory cell means being for: (a) functioning, during times when said first and second voltage lines are energized at a same time and voltage level, in a read/write mode, wherein said bistable memory cell means can be set to either a logical 1 or 0; (b) functioning, during times when said first voltage line is energized at at least one of an earlier time or a higher voltage level than an energization of said second voltage line, in an embedded binary pattern mode wherein each of said bistable memory cell means is set to a logical value corresponding to a selected connection of said first and second sides of said bistable memory cell means to said first or second voltage lines; and (c) functioning, during times when said second voltage line is energized at at least one of an earlier time or a higher voltage level than an energization level of said first voltage line, in a complementary embedded binary pattern mode wherein each of said bistable memory cell means is set to a logical value which is a complement of a logical value which would be obtained from function (b) above.