Patent US4841253A successfully refreshed from Google Patents.
US4841253A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiple spiral inductors for DC biasing of an amplifier
Assignee: Samsung Electronics Co Ltd
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Filing: 1987-04-15
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Granted: 1989-06-20
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Expires: 2007-04-15
Abstract
Abstract A monolithic semiconductor having an on-chip DC biasing including a plurality of series connected spiral inductors connected between the respective biasing and the semiconductor circuit. The spiral inductors provide a low resistive path for the DC biasing while also having a high inductance for isolating the RF signal from the bias sources, thereby improving the low frequency response. The capacitance associated with the individual spirals, however, is significantly less than the capacitance associated with a single spiral inductor having an equivalent inductance of the small series connected spirals; thus the higher frequency response is not degraded while the low frequency response has been improved.
Inventors
- 👤 Carl A. Crabill
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 07:31
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/189; H03F3/19; H03F3/193; H03F3/1935
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
151 words
An amplifying means having an input circuit adapted for receiving electromagnetic wave signals and an output circuit, said amplifying means comprising: a plurality of amplifying stages cascadingly connected between said input circuit and output circuit of said amplifying means wherein said plurality of amplifying stages provides a signal path between said input circuit and output circuit, wherein each of said amplifying stages includes an input portion and an output portion; and inductive means connected outside said signal path and between each output portion of said amplifying stages and a DC bias, said inductive means including at least two spiral inductors connected in series, wherein each of said spiral inductors includes a predetermined inductance for providing a cumulative impedance between the respective output portions of said amplifying stages and said DC bias for isolating said electromagnetic wave signals from said DC bias in a frequency band of 1.5 GHz and 3.0 GHz.
Claim 2
Dependent Claim
151 words
An amplifying means having an input circuit adapted for receiving electromagnetic wave signals and an output circuit, said amplifying means comprising: a plurality of amplifying stages cascadingly connected between said input circuit and output circuit of said amplifying means wherein said plurality of amplifying stages provides a signal path between said input circuit and output circuit, wherein each of said amplifying stages includes an input portion and an output portion; and inductive means connected outside said signal path and between each output portion of said amplifying stages and a DC bias, said inductive means including at least two spiral inductors connected in series, wherein each of said spiral inductors includes a predetermined inductance for providing a cumulative impedance between the respective output portions of said amplifying stages and said DC bias for isolating said electromagnetic wave signals from said DC bias in a frequency band of 1.5 GHz and 3.0 GHz.
Claim 3
Dependent Claim
16 words
The amplifying means of claim 1, wherein said amplifying stages include metal semiconductor field effect transistors.
Claim 4
Dependent Claim
43 words
The amplifying means of claim 1, wherein said spiral inductors further include a cumulative capacitance, wherein said cumulative capacitance is less than a capacitance associated with a single spiral inductor having a substantially same inductance as said spiral inductors of said inductive means.
Claim 5
Dependent Claim
159 words
An amplifying means having an input circuit adapted for receiving electromagnetic wave signals and an output circuit, said amplifying means comprising: a plurality of amplifying stages connected in parallel between said input circuit and output circuit of said amplifying means wherein said plurality of amplifying stages is connected in such a manner as to provide a signal path from the input circuit to the output circuit, and a first inductive means connected outside said signal path and between a first DC bias source and said output circuit of said amplifying means, wherein said inductance means includes at least two spiral inductors connected in series, wherein each of said spiral inductors includes a predetermined inductance for providing a cumulative impedance between the output circuit of said amplifying means and said first DC bias source for isolating said electromagnetic wave signals from said DC bias source and wherein said first inductive means provides DC bias to said plurality of amplifying stages.
Claim 6
Dependent Claim
159 words
An amplifying means having an input circuit adapted for receiving electromagnetic wave signals and an output circuit, said amplifying means comprising: a plurality of amplifying stages connected in parallel between said input circuit and output circuit of said amplifying means wherein said plurality of amplifying stages is connected in such a manner as to provide a signal path from the input circuit to the output circuit, and a first inductive means connected outside said signal path and between a first DC bias source and said output circuit of said amplifying means, wherein said inductance means includes at least two spiral inductors connected in series, wherein each of said spiral inductors includes a predetermined inductance for providing a cumulative impedance between the output circuit of said amplifying means and said first DC bias source for isolating said electromagnetic wave signals from said DC bias source and wherein said first inductive means provides DC bias to said plurality of amplifying stages.
Claim 7
Dependent Claim
52 words
The amplifying means of claim 4, wherein each of said amplifying stages include a metal semiconductor field effect transistor, each transistor having its gate connected to said input of said amplifying means, its drain connected to said output circuit of said amplifying means, and its source connected to a first voltage potential.
Claim 8
Dependent Claim
77 words
The amplifying means of claim 5, further including a second inductive means connected between a second DC bias source and said input circuit of said amplifying means, wherein said inductive means includes at least two spiral inductors connected in series, wherein each of said spiral inductors includes a predetermined inductance for providing a cumulative impedance between said input circuit and said second DC bias source for isolating said electromagnetic wave signals from said second DC bias source.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-19 | 1992-12-19 | 1993-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-19 | 1996-12-19 | 1997-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-19 | 2000-12-19 | 2001-06-20 | $7700.00 | Window Closed / Lapsed |