Output disable control circuit for ECL programmable array logic device

Claim 2

Disable circuitry for disabling an output node of an ECL programmable array logic circuit so that the output node can serve as an input for TTL signals, the disable circuitry comprising: means for generating a control signal; and disable control means operatively connected to the output node and responsive to the control signal for disabling the output node such that TTL signals can be applied to the output node as inputs to the ECL programmable array logic circuit in a first mode.

Claim 3

Disable circuitry as in claim 1 and further including means for sensing the voltage level of the TTL signals on the output node in the first mode without disturbing the output node in a second operating mode of the ECL programmable array logic circuit.

Claim 4

Disable circuitry for disabling output circuitry of an ECL programmable array logic circuit so that the output circuitry can be used as input circuitry to the ECL programmable array logic circuit, the output circuitry including a bipolar output gate transistor having base, emitter and collector, the emitter of the output gate transistor being connected to the output circuitry, the disable circuitry comprising: (a) means for applying a control voltage to the collector of the output gate transistor; and (b) pull down means connected to the base of the output gate transistor and responsive to the control voltage to cause the base of the output gate transistor to be substantially grounded, thereby disabling the output circuitry.

Claim 5

Disable circuitry for disabling output circuitry of an ECL programmable array logic circuit so that the output circuitry can be used as input circuitry to the ECL programmable array logic circuit, the output circuitry including a bipolar output gate transistor having base, emitter and collector, the emitter of the output gate transistor being connected to the output circuitry, the disable circuitry comprising: (a) means for applying a control voltage to the collector of the output gate transistor; and (b) pull down means connected to the base of the output gate transistor and responsive to the control voltage to cause the base of the output gate transistor to be substantially grounded, thereby disabling the output circuitry.

Claim 6

Disable circuitry as in claim 3 wherein the pull down means comprises (a) a first transistor having its emitter and collector commonly connected to the means for applying the control voltage; (b) a second transistor having its base connected to the base of the first transistor, its collector connected to its base and its emitter connected to ground; (c) a third transistor having its base commonly connected to the base of the first transistor and to the means for supplying the control voltage, its emitter connected to the means for supplying the control voltage and its collector commonly connected to the means for supplying the control voltage and to the emitter of the output gate transistor; and (d) a fourth transistor having its base connected to the emitter of the second transistor, its emitter connected to ground and its collector connected to the base of the output gate transistor.

Claim 7

Disable circuitry as in claim 2 wherein the first mode is a programming mode and the second mode is a normal operating mode of the ECL programmable array logic circuit.