Patent US3732576A successfully refreshed from Google Patents.
EP0195489A2
Expired / Lapsed
EP
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Programmable logic array using emitter-coupled logic and input buffer
Assignee: Advanced Micro Devices Inc
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Filing: 1986-03-19
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Granted: —
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Expires: 2006-03-19
Abstract
Abstract A novel ECL Programmable Logic Array (PLA) is provided which operates as an ECL PLA, having ECL voltage level compatible input and output leads, thereby providing a high-speed PLA. A unique programming means is provided which allows the ECL PLA to be programmed using TTL-compatible programming voltage levels, such as are provided by common and inexpensive prior art TTL PLA programmers. In another embodiment higher speed is achieved by the design of each sense amplifier using emitter function logic such that the sense transistor and load functions a cascode amplifier. In another embodiment a lower power PLA device is achieved by utilizing a switched current source pull down means for pulling down the rows of the PLA array. In another embodiment low power and user convenience is achieved by allowing each pair of output terminals to share a predefined set of product terms. In another embodiment of this invention, each output terminal is capable of having its output polarity programmed, in order to provide either a desired product term, or the inverse of that product term.
Inventors
- 👤 Barry A. Hoberman
- 👤 William E. Moss
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 14:59
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0008; H03K19/0016; H03K19/0175; H03K19/018; H03K19/01806; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
97 words
1 . A programmable logic array having ECL array means for combining a plurality of input signals and providing at least one product term, ECL input buffer means for receiving ECL input signals and providing signals to said ECL array, and ECL output buffer means for receiving said at least one product term and providing an ECL output signal corresponding to each said at least one product term, said- programmable logic array characterized by comprising: programming input buffer means for receiving programming input signals having signal levels other than ECL.voltage levels. for programming said programmable logic array.
Claim 2
Dependent Claim
97 words
1 . A programmable logic array having ECL array means for combining a plurality of input signals and providing at least one product term, ECL input buffer means for receiving ECL input signals and providing signals to said ECL array, and ECL output buffer means for receiving said at least one product term and providing an ECL output signal corresponding to each said at least one product term, said- programmable logic array characterized by comprising: programming input buffer means for receiving programming input signals having signal levels other than ECL.voltage levels. for programming said programmable logic array.
Claim 3
Dependent Claim
19 words
A programmable logic array as in Claim 1 further characterized in that said programming input signals have TTL levels.
Claim 4
Dependent Claim
113 words
A logic array for receiving a plurality of input signals and providing one or more product terms, said logic array having a plurality of programming means arranged in a matrix of N rows by M columns, where N and M are positive integers, a plurality of access means, each uniquely associated with one of said programming means, said logic array charaterized by comprising: means for directly testing the programmed state of each of said programming means; and means for providing a verify output signal in response to the programmed state of a programming means being tested, said verify output signal not being dependent on the state of said one or more product terms.
Claim 5
Dependent Claim
113 words
A logic array for receiving a plurality of input signals and providing one or more product terms, said logic array having a plurality of programming means arranged in a matrix of N rows by M columns, where N and M are positive integers, a plurality of access means, each uniquely associated with one of said programming means, said logic array charaterized by comprising: means for directly testing the programmed state of each of said programming means; and means for providing a verify output signal in response to the programmed state of a programming means being tested, said verify output signal not being dependent on the state of said one or more product terms.
Claim 6
Dependent Claim
103 words
A logic array as in Claim 3 further characterized in that said access means comprise a biopolar transistor having a first current handling terminal connected to a supply voltage, a second current handling terminal connected to one end of its associated programming means, and a control terminal connected to receive an input signal, and wherein said means for directly testing comprises a verification transistor having a first current handling terminal connected to a supply voltage, a second current handling terminal connected to said means for providing a verify output signal, and a control terminal connected to said control terminal of said access means.
Claim 7
Dependent Claim
62 words
A logic array as in Claim 4 further characterized in that comprises a plurality of said verification transistors, each uniquely associated with one of said N rows, each of said first current handling terminals of said plurality of verification transistors being connected in common and each of said second current handling terminals of said plurality of verification transistors being connected in common.
Claim 8
Dependent Claim
57 words
A logic array as in Claim 4 further characterized in that said means for providing a verify output signal comprises: a verify output transistor having a control terminal for receiving signals from said verifi cation transistor, a-first current handling terminal connected to a supply voltage, and a second current handling terminal for providing said verify output signal.
Claim 9
Dependent Claim
25 words
A logic array as in Claim 6 further characterized by comprising a verification fuse connected in series with said verification transistor second current handling terminal.
Claim 10
Dependent Claim
57 words
An input buffer including an input terminal for receiving an input signal, and a noninverting output terminal for providing a noninverted output signal, said input buffer characterized by comprising: a current source for providing a pull down current; switch means for switching said pull down current to a selected one of said noninverting and inverting output terminals.
Claim 11
Dependent Claim
57 words
An input buffer including an input terminal for receiving an input signal, and a noninverting output terminal for providing a noninverted output signal, said input buffer characterized by comprising: a current source for providing a pull down current; switch means for switching said pull down current to a selected one of said noninverting and inverting output terminals.
Claim 12
Dependent Claim
37 words
An input buffer as in Claim 8 further characterized in that said selected one of said noninverting and inverting output terminals is that output terminal whose output signal is undergoing a high voltage to low voltage transition.
Claim 13
Dependent Claim
82 words
A programmable logic array including logic array means for combining a plurality of input signals and providing at least one product term on a product term line, and an output buffer, said programmable logic array characterized by comprising: means for connecting said product term to said output buffer comprising a transistor having a control terminal connected to a bias voltage, a first current handling terminal connected to said product term line and a second current handling terminal connected to said output buffer.
Claim 14
Dependent Claim
82 words
A programmable logic array including logic array means for combining a plurality of input signals and providing at least one product term on a product term line, and an output buffer, said programmable logic array characterized by comprising: means for connecting said product term to said output buffer comprising a transistor having a control terminal connected to a bias voltage, a first current handling terminal connected to said product term line and a second current handling terminal connected to said output buffer.
Claim 15
Dependent Claim
39 words
A programmable logic array as in Claim 10 further characterized by comprising a pull up means connected to a selected one of said current handling terminals in order to minimize the voltage swing on said selected current handling terminals.
Claim 16
Dependent Claim
23 words
A programmable logic array as in Claim 11 further characterized in that said pull up means ensures that said transistor never turns off.
Claim 17
Dependent Claim
35 words
A programmable logic array as in Claim 10 further characterized in that said transistor is a PNP transistor; said first current handling terminal is its emitter and said second current handling terminal is its collector.
Claim 18
Dependent Claim
28 words
A programmable logic array as in Claim 10 further characterized in that said output buffer is programmably connected to a selected one of a plurality of product terms.
References Cited (Backward Citations)
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