Data bit synchronizer

Claim 1

A data bit synchronizer for use with a controller in a multiplexing character processor of the type that provides the interchange of information between a central process and a plurality of peripheral devices, each having at least one of a plurality of protocols and at least one of a plurality of interfaces, comprising: RAM means having a plurality of memory address locations for storing a respective control/status word having a plurality of bytes for each of said plurality of peripheral devices; addressing means for uniquely accessing each of the bytes of each control/status words as a function of the respective peripheral device under control of the controller; timing chain means for generating a first sequence of timing pulse signals in response to a falling edge of a controller clock and at substantially the same time generating a second sequence of timing pulse signals in response to a rising edge of the controller clock; said timing chain means is connected to said addressing means to time sequence the accessing of each of said control/status words and said respective bytes thereof; selectable clock divider means connected to said RAM means and said timing chain means for providing a respective timing rate which a selectable division of said controller clock for each of said plurality of peripheral devices; bit clock generating means connected to said RAM means and said selectable clock divider means for logically generating a respective output bit clock signal for each of said plurality of peripheral devices; input data control means connected to said RAM means and multiplexed to a respective receive data signal of each of said plurality of peripheral devices for logically demultiplexing and outputting each respective data bit received from each respective peripheral device to said controller for transfer to said central processor; output data control means connected to said RAM means and to said bit clock synchronizing means for synchronizing each output data bit multiplexed to each respective peripheral device with each respective output bit clock signal; interface control means connected to said RAM means and multiplexed to a respective receive control signal according to the respective interface and protocol of each of said plurality of peripheral devices for logically comparing a current state of each control signal with a previous state thereof and recording each respective change in each respective receive control signal from each respective peripheral device in the respective control/status word therefor; and multiplexer means connected to said addressing means, said output data control means, and said input data control means for multiplexing during a cycle: an output address of one of the plurality of peripheral devices and an input address of one of the plurality of said peripheral devices, at least one output control signal and the output data signal to the peripheral device associated with said output address, and at least one input control signal and the input data signal to the peripheral device associated with said input address.