Patent US4839860A successfully refreshed from Google Patents.
US4839860A
Expired / Lapsed
US
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Semiconductor device having head only memory with differential amplifier
Assignee: Hitachi Microcomputer System Ltd
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Filing: 1986-01-17
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Granted: 1989-06-13
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Expires: 2006-01-17
Abstract
Abstract A semiconductor memory includes a dummy cell for forming a reference potential, a read-only memory cell, and a differential amplifier circuit which receives the reference potential formed by the dummy cell and a signal read out from the memory cell. The differential amplifier circuit is dynamically operated so that the semiconductor memory is made smaller in power consumption and size than conventional units. Moreover, in order to reduce the power consumption, the memory cell is brought into the nonselection state when a predetermined time has passed after being selected. In addition, the semiconductor memory is provided with a compensating circuit in order to make the value of the capacitance connected to a word line for transmitting a selecting signal to the memory cell and the value of the capacitance connected to a dummy word line for transmitting a selecting signal to the dummy cell substantially equal to each other. Thus, the changes in potential of both the selecting signals are made substantially equal to each other. Accordingly, it is possible to reduce malfunctions.
Inventors
- 👤 Takashi Shinoda
- 👤 Kikuo Sakai
- 👤 Masahiro Ogata
- 👤 Hiroshi Kawamoto
- 👤 Yoshiaki Onishi, deceased
- 👤 administratrix by Junko Onishi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 20:10
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1076; G11; G11C; G11C17/00; G11C17/08
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
651 words
A semiconductor memory comprising: a first data line; first and second ground lines; a plurality of memory cells provided between said first data line and said first ground line and between said first data line and said second ground line; a plurality of first word lines each connected with a selecting terminal of one of the memory cells provided between said first data line and said first ground line and a selecting terminal of one of the memory cells provided between said first data line and said second ground line; a second data line; third and fourth ground lines; a plurality of memory cells provided between said second data line and said third ground line and between said second data line and said fourth ground line; a plurality of second word lines each connected with a selecting terminal of one of the memory cells provided between said second data line and said third ground line and a selecting terminal of one of the memory cells provided between said second data line and said fourth ground line; first, second, third and fourth dummy word lines; a first dummy cell provided between said first data line and said first ground line and having a selecting terminal connected to said first dummy word line; a second dummy cell provided between said first data line and said second ground line and having a selecting terminal connected to said second dummy word line; a third dummy cell provided between said second data line and said third ground line and having a selecting terminal connected to said third dummy word line; a fourth dummy cell provided between said second data line and said fourth ground line and having a selecting terminal connected to said fourth dummy word line; first and second compensating circuits connected to said first and second dummy word lines respectively so that a capacitance having a value substantially equal to the value of the capacitance connected to said first word line will be connected to each of said first and second dummy word lines; third and fourth compensating circuits connected to said third and fourth dummy word lines respectively so that a capacitance having a value substantially equal to the value of the capacitance connected to said second word line will be connected to each of said third and fourth dummy word lines; a differential amplifier circuit having one input terminal connected with said first data line and another input terminal connected with said second data line; and a selecting circuit having output terminals connected with said first and second word lines and output terminals connected with said first, second, third and fourth dummy word lines; and wherein when said selecting circuit operates such that the potential of one of said word lines is brougnt to the selection potential of the memory cells and the potential of one of said third and fourth dummy word lines is brought to the selection potential of one of said third and fourth dummy cells, the change in potential at the selecting terminal of one of said third and fourth dummy cells to be selected is made substantially equal to the change in potential at the selecting terminal of a memory cell to be selected, by one of said third and fourth compensating circuits, and when said selecting circuit operates such that the potential of one of said second word lines is brought to the selection potential of the memory cells and the potential of one of said first and second dummy word lines is brought to the selection potential of one of said first and second dummy cells, the change in potential at the selecting terminal of one of said first and second dummy cells to be selected is made substantially equal to the change in potential at the selecting material of a memory cell to be selected, by one of said first and second compensating circuits.
Claim 2
Dependent Claim
651 words
A semiconductor memory comprising: a first data line; first and second ground lines; a plurality of memory cells provided between said first data line and said first ground line and between said first data line and said second ground line; a plurality of first word lines each connected with a selecting terminal of one of the memory cells provided between said first data line and said first ground line and a selecting terminal of one of the memory cells provided between said first data line and said second ground line; a second data line; third and fourth ground lines; a plurality of memory cells provided between said second data line and said third ground line and between said second data line and said fourth ground line; a plurality of second word lines each connected with a selecting terminal of one of the memory cells provided between said second data line and said third ground line and a selecting terminal of one of the memory cells provided between said second data line and said fourth ground line; first, second, third and fourth dummy word lines; a first dummy cell provided between said first data line and said first ground line and having a selecting terminal connected to said first dummy word line; a second dummy cell provided between said first data line and said second ground line and having a selecting terminal connected to said second dummy word line; a third dummy cell provided between said second data line and said third ground line and having a selecting terminal connected to said third dummy word line; a fourth dummy cell provided between said second data line and said fourth ground line and having a selecting terminal connected to said fourth dummy word line; first and second compensating circuits connected to said first and second dummy word lines respectively so that a capacitance having a value substantially equal to the value of the capacitance connected to said first word line will be connected to each of said first and second dummy word lines; third and fourth compensating circuits connected to said third and fourth dummy word lines respectively so that a capacitance having a value substantially equal to the value of the capacitance connected to said second word line will be connected to each of said third and fourth dummy word lines; a differential amplifier circuit having one input terminal connected with said first data line and another input terminal connected with said second data line; and a selecting circuit having output terminals connected with said first and second word lines and output terminals connected with said first, second, third and fourth dummy word lines; and wherein when said selecting circuit operates such that the potential of one of said word lines is brougnt to the selection potential of the memory cells and the potential of one of said third and fourth dummy word lines is brought to the selection potential of one of said third and fourth dummy cells, the change in potential at the selecting terminal of one of said third and fourth dummy cells to be selected is made substantially equal to the change in potential at the selecting terminal of a memory cell to be selected, by one of said third and fourth compensating circuits, and when said selecting circuit operates such that the potential of one of said second word lines is brought to the selection potential of the memory cells and the potential of one of said first and second dummy word lines is brought to the selection potential of one of said first and second dummy cells, the change in potential at the selecting terminal of one of said first and second dummy cells to be selected is made substantially equal to the change in potential at the selecting material of a memory cell to be selected, by one of said first and second compensating circuits.
Claim 3
Dependent Claim
28 words
A semiconductor memory according to claim 1, wherein each of said first, second, third and fourth compensating circuits comprises a capacitance connected to the corresponding dummy word line.
Claim 4
Dependent Claim
69 words
A semiconductor memory according to claim 1, further comprising a plurality of switching MOSFETs provided between said first, second, third and fourth ground lines and a circuit ground potential point respectively, wherein said switching MOSFETs provided between the ground lines connected with the memory cell and dummy cell to be selected and the circuit ground potential point respectively are turned ON by output signals delivered from the selecting circuit.
Claim 5
Dependent Claim
24 words
A semiconductor memory according to claim 3, further comprising precharging elements connected to said first and second data lines for precharging the same respectively.
Claim 6
Dependent Claim
33 words
A semiconductor memory according to claim 1, wherein each of said first, second, third and fourth compensating circuits comprises a MOSFET the gate of which is connected to the corresponding dummy word line.
Claim 7
Dependent Claim
64 words
A semiconductor memory according to claim 5 wherein each of said memory cells comprises a memory MOSFET having a high threshold voltage or low voltage corresponding to the data stored therein, and each of said first, second, third and fourth dummy cells comprises two series-connected MOSFETs each having a low threshold voltage and being substantially equal in size and characteristics to the memory MOSFETs.
Claim 8
Dependent Claim
234 words
A semiconductor memory according to claim 6, wherein: each of said first, second, third and fourth dummy word lines are comprised of first and second parts; the first part of said first dummy word line being connected to the gate of one of the two series connected MOSFETs comprising said first dummy cell, the second part of said first dummy word line being connected to the gate of the other series connected MOSFET of said first dummy cell; the first part of said second dummy word line being connected to the gate of one of the two series connected MOSFETs comprising said second dummy cell, the second part of said second dummy word line being connected to the gate of the other series connected MOSFET of said second dummy cell; the first part of said third dummy word line being connected to the gate of one of the two series connected MOSFETs comprising said third dummy cell, the second part of said third dummy word being connected to the gate of the other series connected MOSFET of said third dummy cell; and the first part of said fourth dummy word line being connected to the gate of one of the two series connected MOSFETs comprising said fourth dummy cell, the second part of said fourth dummy word line being connected to the gate of the other series connected MOSFET of said fourth dummy cell.
Claim 9
Dependent Claim
218 words
A semiconductor memory according to claim 7, wherein: each of said first, second, third and fourth compensating circuits comprises two MOSFETs; the first part of said first dummy word line being connected to the gate of one of the two MOSFETs comprising said first compensating circuit, the second part of said first dummy word line being connected to the gate of the other series connected MOSFET of said first compensating circuit; the first part of said second dummy word line being connected to the gate of one of the two MOSFETs comprising said second compensating circuit, the second part of said second dummy word line being connected to the gate of the other MOSFET of said second compensating circuit; the first part of said third dummy word line being connected to the gate of one of the two MOSFETs comprising said third compensating circuit, the second part of said third dummy word line being connected to the gate of the other MOSFET of said third compensating circuit; and the first part of said fourth dummy word line being connected to the gate of one of the two MOSFETs comprising said fourth compensating circuit, the second part of said fourth dummy word line being connected to the gate of the other series connected MOSFET of said fourth dummy cell.
Claim 10
Dependent Claim
37 words
A semiconductor memory according to claim 8, wherein the two MOSFETs comprising each of said first, second, third and fourth compensating circuits are substantially equal in size and have substantially the same characteristics as the memory MOSFETs.
Claim 11
Dependent Claim
116 words
A semicondutor memory according to claim 9, wherein each of the two MOSFETs comprising each of said first, second, third and fourth compensating circuits is substantially equal in size and characteristics to the memory MOSFETs having a high threshold voltage. the two MOSFETs comprising said first compensating circuit being series-connected between said first data line and second ground line, the two MOSFETs comprising said second compensating circuit being series-connected between said first data line and first ground line, the two MOSFETs comprising said third compensating circuit being series-connected between said second data line and fourth ground line, the two MOSFETs comprising said fourth compensating circuit being series-connected between said second data line and third ground line.
Claim 12
Dependent Claim
27 words
A semiconductor memory according to claim 10, further comprising precharging elements coupled to said first and second data lines for precharging said first and second data lines.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-12 | 1992-12-12 | 1993-06-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-12 | 1996-12-12 | 1997-06-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-12 | 2000-12-12 | 2001-06-13 | $7700.00 | Window Closed / Lapsed |