Patent US4839845A successfully refreshed from Google Patents.
US4839845A
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Method and apparatus for performing a vector reduction
Assignee: Unisys Corp
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Filing: 1986-03-31
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Granted: 1989-06-13
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Expires: 2006-03-31
Abstract
Abstract A vector data reduction to a scalar result in which adjacent elements in the vector are paired and each pair is sequentially reduced in an arithmetic unit organized for so-called pipe line operation is described. The results of each paired pass are stored as result vector elements and these elements are similarly paired, sequentially operated upon, and stored as result vector elements. The process continues until there is but one pair left which is operated upon to produce a singular, scalar result.
Inventors
- 👤 John T. Rusterholz
- 👤 John R. Schomburg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 05:30
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8053; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30036; G06F9/30038
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
275 words
A system for computing vector reductions comprising: a vector memory means for storing and recalling data organized into vectors of elements and capable of simultaneously reading two vector elements and writing one vector element; a first and a second read operand address register means coupled to said vector memory means to provide address location information thereto; a first and a second read operand data staging register means also coupled to said vector memory means to receive and temporarily store operand data read from said vector memory means to thereby provide selective delay by the temporary storage; a first and a second read operand data register means coupled to said first and second read operand data staging register means and also coupled to said vector memory means to selectively receive data from said first and second read operand data staging register means or from said vector memory means; an arithmetic pipeline means coupled to said first and second read operand data register means to receive and combine a first vector element and a second vector element into a combined intermediate result vector element; a write operand address register means coupled to said vector memory means to provide a write address thereto; and a write operand data register means coupled between said arithmetic pipeline means and said vector memory means to provide a return loop for repeatedly returning the combined intermediate result vector element to the vector memory means at the address provided by said write operand address register means until the repeated returning of the combined intermediate result vector element to the vector memory means at the address provided produces a single final result vector element.
Claim 2
Independent Claim
275 words
A system for computing vector reductions comprising: a vector memory means for storing and recalling data organized into vectors of elements and capable of simultaneously reading two vector elements and writing one vector element; a first and a second read operand address register means coupled to said vector memory means to provide address location information thereto; a first and a second read operand data staging register means also coupled to said vector memory means to receive and temporarily store operand data read from said vector memory means to thereby provide selective delay by the temporary storage; a first and a second read operand data register means coupled to said first and second read operand data staging register means and also coupled to said vector memory means to selectively receive data from said first and second read operand data staging register means or from said vector memory means; an arithmetic pipeline means coupled to said first and second read operand data register means to receive and combine a first vector element and a second vector element into a combined intermediate result vector element; a write operand address register means coupled to said vector memory means to provide a write address thereto; and a write operand data register means coupled between said arithmetic pipeline means and said vector memory means to provide a return loop for repeatedly returning the combined intermediate result vector element to the vector memory means at the address provided by said write operand address register means until the repeated returning of the combined intermediate result vector element to the vector memory means at the address provided produces a single final result vector element.
Claim 3
Dependent Claim
55 words
The apparatus as set forth in claim 1, wherein said first and said second read operand address register means and said first write operand address register means operate together to simultaneously permit the reading of two vector elements from said vector memory means and the writing of one vector elements into said vector memory means.
Claim 4
Dependent Claim
47 words
The apparatus as set forth in claim 2 wherein the vector memory means includes further means for allowing the simultaneous reading of two vector elements and the writing of one vector element to be directed to different elements of different vectors stored in said vector memory means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-12 | 1992-12-12 | 1993-06-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-12 | 1996-12-12 | 1997-06-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-12 | 2000-12-12 | 2001-06-13 | $7700.00 | Window Closed / Lapsed |