Patent US4839787A successfully refreshed from Google Patents.
US4839787A
Expired / Lapsed
US
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Integrated high voltage generating system
Assignee: Panasonic Holdings Corp
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Filing: 1988-05-20
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Granted: 1989-06-13
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Expires: 2008-05-20
Abstract
Abstract This invention relates to an integrated high voltage generating system provided with a charge pump for raising the input power supply voltage sequentially while transferring the electric charges of the capacitors on a stage by stage basis, by serially connecting unit circuits composed of diode elements and capacitors, and supplying clock signals of mutually opposite phases to adjacent capacitors. Source and drain electrodes of a MOS transistor are connected between the first power supply output terminal and a second power supply output terminal, and the gate electrode of this MOS transistor is connected to the input end of any one of the unit circuits of the charge pump, wherein the voltage of the first power supply output terminal is stepped down depending on the voltage applied to the gate electrode of the MOS transistor, and is delivered to the second power supply output terminal. In this way, since the voltage is not stepped down using a dividing circuit, a potential between input power supply voltage and the first input power supply voltage can be obtained from the second power supply output terminal, without consuming unnecessary current and without causing the chip area to be increased.
Inventors
- 👤 Makoto Kojima
- 👤 Hirozumi Misaki
- 👤 Yasuyuki Okada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 17:54
CPC Classifications
H; H02; H02M; H02M1/00; H02M1/08; H02M3/00; H02M3/02; H02M3/04; H02M3/06; H02M3/07; H02M3/073; H02M1/0083; H02M1/009
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
307 words
An integrated high voltage generating system comprising: a charge pump composed of plural unit circuits, each of said plural unit circuits having a capacitor and a diode element, wherein one end of said capacitor is connected to an input end of said diode element in each of said plural unit circuits, and wherein each of said plural unit circuits represents a stage of said charge pump, and wherein said plural unit circuits are uniformly arranged according to a polarity of each diode element, and wherein an output end of said diode element of each preceding stage is sequentially connected to the input end of said diode element of each succeeding stage, whereby, when clock signals of mutually opposite phases are respectively applied to the other end of each capacitor of adjacent said plural unit circuits, an electric charge stored in said capacitor of each preceding stage is sequentially transferred to said capacitor of each succeeding stage, thereby raising a voltage level on a stage by stage basis; a power supply input terminal connected to a first stage of said charge pump at said input end of said diode element of a first unit circuit; a first power supply output terminal connected to a final stage of said charge pump at said output end of said diode element of a final unit circuit; a second power supply output terminal; and a first MOS transistor having source and drain electrodes connected between said first and second power supply output terminals, and having a gate electrode connected at the input end of any one of said plural unit circuits of said charge pump, wherein a voltage of said first power supply output terminal is stepped down according to a voltage applied to said gate electrode, and wherein said stepped down voltage is delivered to said second power supply output terminal.
Claim 2
Dependent Claim
307 words
An integrated high voltage generating system comprising: a charge pump composed of plural unit circuits, each of said plural unit circuits having a capacitor and a diode element, wherein one end of said capacitor is connected to an input end of said diode element in each of said plural unit circuits, and wherein each of said plural unit circuits represents a stage of said charge pump, and wherein said plural unit circuits are uniformly arranged according to a polarity of each diode element, and wherein an output end of said diode element of each preceding stage is sequentially connected to the input end of said diode element of each succeeding stage, whereby, when clock signals of mutually opposite phases are respectively applied to the other end of each capacitor of adjacent said plural unit circuits, an electric charge stored in said capacitor of each preceding stage is sequentially transferred to said capacitor of each succeeding stage, thereby raising a voltage level on a stage by stage basis; a power supply input terminal connected to a first stage of said charge pump at said input end of said diode element of a first unit circuit; a first power supply output terminal connected to a final stage of said charge pump at said output end of said diode element of a final unit circuit; a second power supply output terminal; and a first MOS transistor having source and drain electrodes connected between said first and second power supply output terminals, and having a gate electrode connected at the input end of any one of said plural unit circuits of said charge pump, wherein a voltage of said first power supply output terminal is stepped down according to a voltage applied to said gate electrode, and wherein said stepped down voltage is delivered to said second power supply output terminal.
Claim 3
Dependent Claim
42 words
An integrated high voltage generating system according to claim 1, further comprising: an additional diode element connected between the input end of any one of said plural unit circuits of said charge pump and said gate electrode of said first MOS transistor.
Claim 4
Dependent Claim
30 words
An integrated high voltage generating system according to claim 2, further comprising: a smoothing capacitor connected between said gate electrode of said first MOS transistor and a reference potential point.
Claim 5
Dependent Claim
72 words
An integrated high voltage generating system according to claim 1, further comprising: a second MOS transistor having drain and source electrodes connected between the input end of any one of said plural unit circuits of said charge pump and said gate electrode of said first MOS transistor, and having a gate electrode connected to the input terminal of a unit circuit that is preceeding said any one of said plural unit circuits.
Claim 6
Dependent Claim
30 words
An integrated high voltage generating system according to claim 4, further comprising: a smoothing capacitor connected between said gate electrode of said first MOS transistor and a reference potential point.
Claim 7
Dependent Claim
68 words
An integrated high voltage generating system according to claim 1 further comprising: a voltage detection circuit connected to said first power supply output terminal of said charge pump in order to detect if the voltage of said first power supply output terminal has exceeded a predetermined value; and means for maintaining the voltage of said first power supply output terminal of the charge pump at said predetermined value.
Claim 8
Dependent Claim
68 words
An integrated high voltage generating system according to claim 4, further comprising: a voltage detection circuit connected to said first power supply output terminal of said charge pump in order to detect if the voltage of said first power supply output terminal has exceeded a predetermined value; and means for maintaining the voltage of said first power supply output terminal of the charge pump at said predetermined value.
Claim 9
Dependent Claim
340 words
Integrated high voltage generating system comprising: first and second charge pumps individually composed of plural unit circuits, each of said plural unit circuits having a capacitor and a diode element, wherein one end of said capacitor is connected to an input end of said diode element in each of said plural unit circuits, and wherein each of said plural unit circuits represents a stage of each charge pump, and wherein said plural unit circuits are uniformly arranged according to a polarity of said diode elements, and wherein an output end of said diode element of each preceding stage is sequentially connected to the input end of said diode element of each succeeding stage, whereby, when clock signals having mutually opposite phases are respectively applied to the other end of each capacitor of adjacent said plural unit circuits, an electric charge stored in said capacitor of each preceding stage is sequentially transferred to said capacitor of each succeeding stage, thereby raising a voltage level on a stage by stage basis, and wherein said clock signals having mutually opposite phases are respectively supplied to said first and second charge pumps; a power supply input terminal connected to a first stage of said first and second charge pumps at the input end of said diode element of a first unit circuit; a first power supply output terminal connected to a final stage of said first and second charge pumps at the output end of said diode element of a final unit circuit; a second power supply output terminal; a first MOS transistor having drain and source electrodes respectively connected between said first and second power supply output terminals, and having a gate electrode connected to the input end of any one of the unit circuits of said first charge pump; and a second MOS transistor having drain and source electrodes respectively connected between said first and second power supply output terminals, and having a gate electrode connected to the input end of any one of the unit circuits of said second charge pump.
Claim 10
Dependent Claim
340 words
Integrated high voltage generating system comprising: first and second charge pumps individually composed of plural unit circuits, each of said plural unit circuits having a capacitor and a diode element, wherein one end of said capacitor is connected to an input end of said diode element in each of said plural unit circuits, and wherein each of said plural unit circuits represents a stage of each charge pump, and wherein said plural unit circuits are uniformly arranged according to a polarity of said diode elements, and wherein an output end of said diode element of each preceding stage is sequentially connected to the input end of said diode element of each succeeding stage, whereby, when clock signals having mutually opposite phases are respectively applied to the other end of each capacitor of adjacent said plural unit circuits, an electric charge stored in said capacitor of each preceding stage is sequentially transferred to said capacitor of each succeeding stage, thereby raising a voltage level on a stage by stage basis, and wherein said clock signals having mutually opposite phases are respectively supplied to said first and second charge pumps; a power supply input terminal connected to a first stage of said first and second charge pumps at the input end of said diode element of a first unit circuit; a first power supply output terminal connected to a final stage of said first and second charge pumps at the output end of said diode element of a final unit circuit; a second power supply output terminal; a first MOS transistor having drain and source electrodes respectively connected between said first and second power supply output terminals, and having a gate electrode connected to the input end of any one of the unit circuits of said first charge pump; and a second MOS transistor having drain and source electrodes respectively connected between said first and second power supply output terminals, and having a gate electrode connected to the input end of any one of the unit circuits of said second charge pump.
Claim 11
Dependent Claim
59 words
An integrated high voltage generating system of claim 8, further comprising: a voltage detection circuit connected to said first power supply output terminal in order to detect if the voltage of said first power supply output terminal has exceeded a predetermined value; and means for maintaining the voltage of said first power supply output terminal at said predetermined value.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-12 | 1992-12-12 | 1993-06-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-12 | 1996-12-12 | 1997-06-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-12 | 2000-12-12 | 2001-06-13 | $7700.00 | Window Closed / Lapsed |