Circuit for multiplying a pump clock voltage

Claim 2

A voltage multiplier circuit having an input node and an output node, comprising: transfer clock means for providing a transfer clock signal; pump clock means for providing a pump clock signal having high and low levels; pump capacitor means for capacitively coupling said pump clock means to said output node; switching means for selectively coupling the output node to or isolating it from the input node in response to said transfer clock signal so that said switching means couples said input node to said output node during an interval when said pump clock is at said high level to equalize the potential between said input and output nodes, and to isolate said nodes when the potential at the output node is lower than the potential at the input node.

Claim 3

The invention of claim 1 further comprising rectifying means for rectifying the circuit output signal at said output node to provide a substantially constant output voltage under unloaded conditions.

Claim 4

The invention of claim 1 wherein said input node is connected to ground.

Claim 5

The invention of claim 1 wherein said switching means comprises transistor means having first and second electrodes coupled respectively to said input and output nodes, and a control gate coupled to said transfer clock means.

Claim 6

A voltage multiplier circuit having an input node and an output node, comprising: transfer clock means for providing a transfer clock signal; pump clock means for providing a pump clock signal having high and low levels; pump capacitor means for capacitively coupling said pump clock means to said output node; and switching means for selectively coupling the output node to the input node in response to said transfer clock signal, said switching means comprising transistor means having first and second electrodes coupled respectively to said input and output nodes, and a control gate capacitively coupled to said transfer clock means; whereby said transfer clock signal and said switching means are cooperatively adapted so that said switching means couples said input node to said output node during an interval when said pump clock signal is at said high level so as to equalize the potential between said first and second node, and isolates said input and output nodes when the potential at the output node is lower than the potential at the input node.

Claim 7

A voltage multiplier circuit having an input node and an output node, comprising: transfer clock means for providing a transfer clock signal; pump clock means for providing a pump clock signal having high and low levels; pump capacitor means for capacitively coupling said pump clock means to said output node; and switching means for selectively coupling the output node to the input node in response to said transfer clock signal, said switching means comprising transistor means having first and second electrodes coupled respectively to said input and output nodes, and a control gate capacitively coupled to said transfer clock means; whereby said transfer clock signal and said switching means are cooperatively adapted so that said switching means couples said input node to said output node during an interval when said pump clock signal is at said high level so as to equalize the potential between said first and second node, and isolates said input and output nodes when the potential at the output node is lower than the potential at the input node.

Claim 8

The invention of claim 5 further comprising resetting means for selectively resetting the potential of said control gate to the potential of said input node.

Claim 9

The invention of claim 6 wherein said resetting means comprises a second transistor having source and drain electrodes coupled respectively to the input node and the control gate, and a second control gate capacitively coupled to said pump clock means.

Claim 10

The invention of claim 7 further comprising means for selectively resetting the potential of said second control gate to the potential of said input node.

Claim 11

The invention of claim 8 wherein said means for selectively resetting the potential of said second control gate comprises third transistor means having first and second electrodes coupling the second control gate to said input node, and a control gate capacitively coupled to said transfer clock means.

Claim 12

A voltage multiplier circuit for responding to nonoverlapping first and second pump clock signals, each having high and low levels, and nonoverlapping first and second transfer clock signals, each having high and low levels, an output voltage more negative than the low state of the clock signal, said circuit comprising: a plurality of cascaded multiplier stages, each stage having an input node and an output node, the output node of the odd ones of the stages being capacitively coupled to receive said first pump clock signal and the output node of the even ones of the stages being capacitively coupled to receive said second pump clock signal, each stage further comprising: switching means responsive to one of said first and second transfer clock signals for selectively coupling the output node to the input node during each interval in the cycle of said respective first and second pump clock signals when said respective pump clock signal is at said high level, and for isolating said input node from said output node when said output node is at a potential lower than the potential of said input node.

Claim 13

A voltage multiplier circuit for responding to nonoverlapping first and second pump clock signals, each having high and low levels, and nonoverlapping first and second transfer clock signals, each having high and low levels, an output voltage more negative than the low state of the clock signal, said circuit comprising: a plurality of cascaded multiplier stages, each stage having an input node and an output node, the output node of the odd ones of the stages being capacitively coupled to receive said first pump clock signal and the output node of the even ones of the stages being capacitively coupled to receive said second pump clock signal, each stage further comprising: switching means responsive to one of said first and second transfer clock signals for selectively coupling the output node to the input node during each interval in the cycle of said respective first and second pump clock signals when said respective pump clock signal is at said high level, and for isolating said input node from said output node when said output node is at a potential lower than the potential of said input node.

Claim 14

The invention of claim 10 wherein said first and second clock signals are substantially 180° out of phase.

Claim 15

The invention of claim 10 wherein the switching means of each respective stage is controlled by a particular one of non-overlapping first and second transfer clock signals, said first transfer clock signals being applied to the switching means of the odd stages so as to cause said switching means to couple the input node to the output node of the respective stage during the interval when the respective first pump clock signal applied to the output node is at its high state, and said second transfer clock signal being applied to the switching means of the even stages so as to cause said switching means of said even stages to couple the input node to the output node of the respective stage during the interval when the respective second pump clock signal applied to the output node is at its high state.

Claim 16

The invention of claim 5 wherein the switching means of each respective stage comprises a transistor whose control gate is coupled to receive its respective transfer clock signal and having first and second electrodes coupled to respective ones of the input and output nodes.

Claim 17

The invention of claim 13 wherein the respective transfer clock is capacitively coupled to the control gate of the transistor means of each respective stage, and each stage further comprises means for selectively resetting the potential of said respective control gate to the potential of the respective input node.

Claim 18

The invention of claim 14 wherein said means for selectively resetting the potential comprises a second transistor having first and second electrodes coupled to said input node and said control gate, and having second control gate means capacitively coupled to its respective pump clock signal.

Claim 19

A voltage multiplier for integrated circuits for generating an output voltage from a pump clock signal having periodic high and low level, comprising at least one stage, each stage comprising: pump capacitor means for coupling said pump clock signal to the output node of the stage; field effect transistor means having source and drain electrodes coupling said output node to the input node of the stage, and a control gate coupled to receive a transfer clock signal; the transfer clock signal being cooperatively arranged with said pump clock signal so as to gate the transistor to the conductive level during the time intervals when said pump clock signal is at its high level to equalize the potential at said input and output nodes, and so that the transistor is in the nonconductive level when the pump clock signal is at its low level; whereby each stage of said multiplier circuit is adapted to generate a potential at the output node substantially equal to -(V H -V IN ), where V IN represents the potential at the input node and V H represents the potential of the pump clock signal at the high level.

Claim 20

A voltage multiplier for integrated circuits for generating an output voltage from a pump clock signal having periodic high and low level, comprising at least one stage, each stage comprising: pump capacitor means for coupling said pump clock signal to the output node of the stage; field effect transistor means having source and drain electrodes coupling said output node to the input node of the stage, and a control gate coupled to receive a transfer clock signal; the transfer clock signal being cooperatively arranged with said pump clock signal so as to gate the transistor to the conductive level during the time intervals when said pump clock signal is at its high level to equalize the potential at said input and output nodes, and so that the transistor is in the nonconductive level when the pump clock signal is at its low level; whereby each stage of said multiplier circuit is adapted to generate a potential at the output node substantially equal to -(V H -V IN ), where V IN represents the potential at the input node and V H represents the potential of the pump clock signal at the high level.

Claim 21

The invention of claim 16 wherein transfer clock signal is capacitively coupled to said control gate of said transistor, and further comprising means for setting the potential at the control gate to the potential at the input node when said pump clock signal is at the low state.

Claim 22

The invention of claim 17 wherein means for setting the potential at the control gate comprises second field effect transistor means having source and drain electrodes respectively coupled to said control gate and said input node, and a second control gate capacitively coupled to the pump clock signal.

Claim 23

The invention of claim 18 wherein said second control gate is coupled to receive said pump clock signal by a second capacitor means, whereby said second control gate is isolated from said output node.

Claim 24

The invention of claim 16 wherein said voltage multiplier comprises a plurality of N stages, the input node of the first stage being connected to ground, and the input node of each succeeding stage being coupled to the output node of the preceding stage, and wherein adjacent ones of said stages are clocked by non-overlapping pump and transfer clock signals.

Claim 25

The invention of claim 20 further comprising an output rectifier stage coupled to the output node of the last stage N, whereby said circuit is adapted to generate an output voltage of -NV H under steady-state, capacitively loaded conditions.

Claim 26

The invention of claim 16 wherein said transfer clock signals has first and second states, the first state at ground potential and the second state at a supply potential for the integrated circuit.