Tri-state output circuit

Claim 1

A tri-state output circuit which comprises: (a) an input section having a NOR gate circuit receptive of an input signal and a tri-state signal for taking an inverse OR logical sum, and an invertor circuit receptive of the tri-state signal for producing an inverted signal thereof, each of said circuits consisting of a plurality of complementary field effect transistors; (b) a control section having a first field effect transistor having a first conductivity type and a second field effect transistor having a second conductivity type, each of the gate terminals thereof being commonly connected to an output terminal of said invertor circuit, each of the source terminals thereof being connected to either a power supply or to a ground potential respectively, a third field effect transistor of said second conductivity type having its gate terminal being connected to an output terminal of the NOR gate circuit and its source being connected to the ground potential, a first electric current control circuit having a plurality of field effect transistors of said second conductivity type, coupled to said first, second, and third field effect transistors and a second electric current control circuit having a plurality of field effect transistors of said second conductivity type, each gate of said transistors being connected to either an input terminal or to the tri-state terminal respectively; and (c) an output section having first and second output transistors, and third and fourth transistors, said third transistor being Darlington-connected to said first output transistor, with its base terminal connected to one of the junction points of the first electric current control circuit, said fourth transistor being Darlington-connected to said second output transistor, with its base terminal connected to one of the junction points of the second electric current control circuit.