US4839540A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Tri-state output circuit
Assignee: Toshiba Corp
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Filing: 1988-03-31
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Granted: 1989-06-13
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Expires: 2008-03-31
Abstract
Abstract A tri-state output circuit comprising an input section having complementary field effect transistors which constitute NOR gate and investor circuits, a control section having first and second current control circuits, and an output section having bipolar transistors wherein an input signal and a tri-state signal are logically processed in the input section and its result applied to the control section. Then, the switching operations of the output section and a high impedance condition of the output terminal of the tri-state output circuit are controlled by the control section consisting of a plurality of complementary FETs, thereby achieving a low power consumption, a high load driving capability, and a high speed operation.
Inventors
- 👤 Masaji Ueno
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 06:47
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/20; H03K19/02; H03K19/08; H03K19/094; H03K19/09425; H03K19/09429; H03K19/0944; H03K19/09448
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
292 words
A tri-state output circuit which comprises: (a) an input section having a NOR gate circuit receptive of an input signal and a tri-state signal for taking an inverse OR logical sum, and an invertor circuit receptive of the tri-state signal for producing an inverted signal thereof, each of said circuits consisting of a plurality of complementary field effect transistors; (b) a control section having a first field effect transistor having a first conductivity type and a second field effect transistor having a second conductivity type, each of the gate terminals thereof being commonly connected to an output terminal of said invertor circuit, each of the source terminals thereof being connected to either a power supply or to a ground potential respectively, a third field effect transistor of said second conductivity type having its gate terminal being connected to an output terminal of the NOR gate circuit and its source being connected to the ground potential, a first electric current control circuit having a plurality of field effect transistors of said second conductivity type, coupled to said first, second, and third field effect transistors and a second electric current control circuit having a plurality of field effect transistors of said second conductivity type, each gate of said transistors being connected to either an input terminal or to the tri-state terminal respectively; and (c) an output section having first and second output transistors, and third and fourth transistors, said third transistor being Darlington-connected to said first output transistor, with its base terminal connected to one of the junction points of the first electric current control circuit, said fourth transistor being Darlington-connected to said second output transistor, with its base terminal connected to one of the junction points of the second electric current control circuit.
Claim 2
Dependent Claim
292 words
A tri-state output circuit which comprises: (a) an input section having a NOR gate circuit receptive of an input signal and a tri-state signal for taking an inverse OR logical sum, and an invertor circuit receptive of the tri-state signal for producing an inverted signal thereof, each of said circuits consisting of a plurality of complementary field effect transistors; (b) a control section having a first field effect transistor having a first conductivity type and a second field effect transistor having a second conductivity type, each of the gate terminals thereof being commonly connected to an output terminal of said invertor circuit, each of the source terminals thereof being connected to either a power supply or to a ground potential respectively, a third field effect transistor of said second conductivity type having its gate terminal being connected to an output terminal of the NOR gate circuit and its source being connected to the ground potential, a first electric current control circuit having a plurality of field effect transistors of said second conductivity type, coupled to said first, second, and third field effect transistors and a second electric current control circuit having a plurality of field effect transistors of said second conductivity type, each gate of said transistors being connected to either an input terminal or to the tri-state terminal respectively; and (c) an output section having first and second output transistors, and third and fourth transistors, said third transistor being Darlington-connected to said first output transistor, with its base terminal connected to one of the junction points of the first electric current control circuit, said fourth transistor being Darlington-connected to said second output transistor, with its base terminal connected to one of the junction points of the second electric current control circuit.
Claim 3
Dependent Claim
44 words
The tri-state output circuit as claimed in claim 1 wherein a specific type of a first diode and a current limiting resistor connected in series is provided between the power supply and the junction point of the collectors of the first and third transistors.
Claim 4
Dependent Claim
38 words
The tri-state output circuit as claimed in claim 1 wherein a specific type of a second diode is provided in parallel with the second transistor between an output terminal of the tri-state output circuit and the ground potential.
Claim 5
Dependent Claim
29 words
The tri-state output circuit as claimed in claim 1 wherein said first conductivity type is a P-channel type FET and said second conductivity type is a N-channel type FET.
Claim 6
Dependent Claim
106 words
The tri-state output circuit as claimed in claim 1 wherein said first electric current control circuit comprises fourth and fifth field effect transistors of the second conductivity type having their gate terminals connected to the input terminal, respectively, and sixth and seventh field effect transistors of the second conductivity type having their gate terminals connected to the tri-state terminal, respectively, said fourth and seventh field effect transistors as well as said fifth and sixth field effect transistors being connected in series, while said fourth and sixth field effect transistors as well as the fifth and seventh field effect transistors being connected in parallel with each other.
Claim 7
Dependent Claim
106 words
The tri-state output circuit as claimed in claim 1 wherein said second electric current control circuit comprises fourth and fifth field effect transistors of the second conductivity type having their gate terminals connected to the input terminal, respectively, and sixth and seventh field effect transistors of the second conductivity type having their gate terminals connected to the tri-state terminal, respectively, said fourth and seventh field effect transistors as well as said fifth and sixth field effect transistors being connected in series, while said fourth and sixth field effect transistors as well as the fifth and seventh field effect transistors being connected in parallel with each other.
Claim 8
Dependent Claim
25 words
The tri-state output circuit as claimed in claim 1 wherein said complementary field effect transistors are P-channel conductivity type and N-channel conductivity type FET transistors.
Claim 9
Dependent Claim
26 words
The tri-state output circuit as claimed in claim 1 wherein said second, third, and fourth transistors of the output section are Schottky barrier NPN transistors respectively.
Claim 10
Dependent Claim
20 words
The tri-state output circuit as claimed in claim 2 wherein said first and second diodes are Schottky barrier type diodes.
Claim 11
Dependent Claim
20 words
The tri-state output circuit as claimed in claim 3 wherein said first and second diodes are Schottky barrier type diodes.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-12 | 1992-12-12 | 1993-06-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-12 | 1996-12-12 | 1997-06-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-12 | 2000-12-12 | 2001-06-13 | $7700.00 | Window Closed / Lapsed |