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Patent US4837173A successfully refreshed from Google Patents.
US4837173A
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N-channel MOS transistors having source/drain regions with germanium
Assignee: NXP USA Inc
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Filing: 1987-07-13
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Granted: 1989-06-06
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Expires: 2007-07-13
Abstract
Abstract Metal-oxide-semiconductor (MOS) transistors with n-type source/drain regions also having germanium-doped regions in or near the source/drains. The presence of germanium near or at the location of phosphorus in graded source drains (GSDs), lightly doped drains (LDDs) and double diffused drains (DDDs) gives a better profile of the drain region with a reduced junction depth than that obtainable with phosphorus or particularly phosphorus and arsenic together. Good grading of the drain junction to avoid hot carrier instability or hot carrier injection problems is obtained along with shallow source junctions, which minimizes lateral dopant diffusion and decreases the distance between n- and n+ regions in GSDs and LDDs.
Inventors
- 👤 John R. Alvis
- 👤 James R. Pfiester
- 👤 Orin W. Holland
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 12:47
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D30/601; H10D30/605; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D62/60; H10D62/80; H10D62/83; H10D62/834; H10P30/208
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
67 words
A process for providing a doped n-type region in a semiconductor substrate, comprising the steps of: providing a semiconductor substrate having a surface; introducing germanium atoms into a first region of the semiconductor substrate, and introducing phosphorus into a second region of the semiconductor substrate, where said first region and said second region are in a relationship of overlapping but not coextensive; and annealing the semiconductor substrate.
Claim 2
Dependent Claim
67 words
A process for providing a doped n-type region in a semiconductor substrate, comprising the steps of: providing a semiconductor substrate having a surface; introducing germanium atoms into a first region of the semiconductor substrate, and introducing phosphorus into a second region of the semiconductor substrate, where said first region and said second region are in a relationship of overlapping but not coextensive; and annealing the semiconductor substrate.
Claim 3
Dependent Claim
16 words
The process of claim 1 wherein the germanium and phosphorus introductions are conducted by ion implantation.
Claim 4
Dependent Claim
16 words
The process of claim 2 wherein the only species used for the germanium introduction is Ge.
Claim 5
Dependent Claim
141 words
A process for providing a doped n-type region in a semiconductor substrate as a source/drain region for an n-channel MOSFET, comprising the steps of: providing a semiconductor substrate having a surface; providing a thin dielectric layer on the surface of the semiconductor substrate; providing a patterned gate of conductive material on the thin dielectric layer, where the gate has opposite sides; introducing germanium atoms into a first region of the semiconductor substrate on at least one side of the gate, and introducing phosphorus atoms into a second region of the semiconductor substrate, where said first region and said second region are in a relationship of overlapping but not coextensive; and annealing the semiconductor substrate to form source/drain regions in the semiconductor substrate beneath the opposite sides of the gate defining a channel in the semiconductor substrate between the two source/drain regions.
Claim 6
Dependent Claim
141 words
A process for providing a doped n-type region in a semiconductor substrate as a source/drain region for an n-channel MOSFET, comprising the steps of: providing a semiconductor substrate having a surface; providing a thin dielectric layer on the surface of the semiconductor substrate; providing a patterned gate of conductive material on the thin dielectric layer, where the gate has opposite sides; introducing germanium atoms into a first region of the semiconductor substrate on at least one side of the gate, and introducing phosphorus atoms into a second region of the semiconductor substrate, where said first region and said second region are in a relationship of overlapping but not coextensive; and annealing the semiconductor substrate to form source/drain regions in the semiconductor substrate beneath the opposite sides of the gate defining a channel in the semiconductor substrate between the two source/drain regions.
Claim 7
Dependent Claim
16 words
The process of claim 4 wherein the germanium and phosphorus introductions are conducted by ion implantation.
Claim 8
Dependent Claim
16 words
The process of claim 5 wherein the only species used for the germanium introduction is Ge.
Claim 9
Dependent Claim
121 words
A process for forming a source/drain region for an n-channel transistor on a semiconductor integrated circuit comprising the steps of: providing a semiconductor substrate; providing a thin dielectric layer on the substrate; providing a patterned gate on the thin dielectric layer where the gate has opposite sides; implanting phosphorus in a region of the semiconductor substrate aligned to at least one of the opposite sides of the gate; providing a sidewall spacer around the patterned gate; implanting germanium and arsenic into the semiconductor into the semiconductor substrate aligned with the sidewall spacer; and annealing the substrate to form source/drain regions in the semiconductor substrate on either side of the gate, the source/drain regions defining a channel in the substrate between them.
Claim 10
Dependent Claim
121 words
A process for forming a source/drain region for an n-channel transistor on a semiconductor integrated circuit comprising the steps of: providing a semiconductor substrate; providing a thin dielectric layer on the substrate; providing a patterned gate on the thin dielectric layer where the gate has opposite sides; implanting phosphorus in a region of the semiconductor substrate aligned to at least one of the opposite sides of the gate; providing a sidewall spacer around the patterned gate; implanting germanium and arsenic into the semiconductor into the semiconductor substrate aligned with the sidewall spacer; and annealing the substrate to form source/drain regions in the semiconductor substrate on either side of the gate, the source/drain regions defining a channel in the substrate between them.
Claim 11
Dependent Claim
19 words
The process of claim 1 wherein the channel in the substrate has a length of one micron or less.
Claim 12
Dependent Claim
17 words
The process of claim 7 wherein the species implanted for the germanium ion implant is germanium only.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-05 | 1992-12-05 | 1993-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-05 | 1996-12-05 | 1997-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-05 | 2000-12-05 | 2001-06-06 | $7700.00 | Window Closed / Lapsed |