Electron gas hole gas tunneling transistor device

Claim 2

A semiconductor device comprising: a first semiconductor layer; a second semiconductor layer; a third semiconductor layer being formed between the first and second semiconductor layers, having first carriers at a first boundary of the first and the third semiconductor layers and second carriers at a second boundary of the second and the third semiconductor layers, and having a band gap narrower than those of the first and the second semiconductor layers so that band discontinuities in conduction bands and valence bands of the three layers form barriers to the first and second carriers; a first electrode being disposed so as to be electrically connected to the first boundary and substantially without being connected to the second boundary; a second electrode being disposed so as to be electrically connected to the second boundary and substantially without being connected to the first boundary; and a third electrode for applying an electrical field to the third semiconductor layer so as to effect in controlling flow of a tunneling current of the first and the second carriers between the first and the second boundaries in accordance with the electric field in the third semiconductor layer.

Claim 3

A semiconductor device as claimed in claim 1, wherein said first semiconductor layer is made of a semiconductor material principally composed of GaAs, said second semiconductor layer is made of a semiconductor material principally composed of Al x Ga 1-x As, and said third semiconductor layer is made of a semiconductor material principally composed of Ge.

Claim 4

A semiconductor deice as claimed in claim 1, wherein said first semiconductor layer is made of a semiconductor material principally composed of InP, said second semiconductor layer is made of a semiconductor material principally composed of In 0 .52 Al 0 .48 As, and said third semiconductor layer is made of a semiconductor material principally composed of In 0 .53 Ga 0 .47 As.

Claim 5

A semiconductor device according to claim 1, wherein the first and the second carriers are two dimensional hole and electron gas layers, respectively.

Claim 6

A semiconductor device according to claim 4, wherein the third semiconductor layer has a p + doped region and an n + doped region so as to form a p + /n + junction therein.

Claim 7

A semiconductor device according to claim 4, wherein the third semiconductor layer is undoped, and the first and the second semiconductor layers are p + and n + doped layers, respectively.

Claim 8

A semiconductor device according to claim 6, wherein the first semiconductor layer is formed on a substrate.

Claim 9

A semiconductor device according to claim 5, wherein the first semiconductor layer includes a buffer layer formed on a substrate.

Claim 10

A semiconductor device according to claim 1, wherein the first semiconductor layer is a substrate.

Claim 11

A semiconductor device according to claim 9, wherein said first semiconductor layer is made of a semiconductor material principally composed of GaAs, said second semiconductor layer is made of a semiconductor material principally composed of Al x Ga 1-x As, and said third semiconductor layer is made of a semiconductor material principally composed of Ge.

Claim 12

A semiconductor device according to claim 9, wherein said first semiconductor layer is made of a semiconductor material principally composed of InP, said second semiconductor layer is made of a semiconductor material principally composed of In 0 .52 Al 0 .48 As, and said third semiconductor layer is made of a semiconductor material principally composed of In 0 .53 Ga 0 .47 As.

Claim 13

A semiconductor device according to claim 1, wherein said first, second and third electrodes comprise drain, source and gate electrodes of a high-frequency, low-noise field-effect transistor device.

Claim 14

A high-frequency and low-noise semiconductor transistor device comprising: first, second and third semiconductor layers vertically disposed in an arrangement wherein said third semiconductor layer is formed on said first semiconductor layer and said second semiconductor layer is formed on said third semiconductor layer, said third semiconductor layer having first carriers at a first heterojunction formed by said first and third semiconductor layers and second carriers at a second heterojunction formed by said second and third semiconductor layers and having a band gap narrower than those of said first and second semiconductor layers so that band discontinuities in conduction bands and valence bands of the three layers form barriers to said first and second carriers; a first electrode having a contact region disposed in a portion of said third semiconductor layer and extending to a main surface of said device so as to be electrically connected to said first heterojunction and substantially without being connected to said second heterojunction; a second electrode having a contact region disposed in a portion of said third semiconductor layer and extending to the main surface of said device so as to be substantially electrically connected to said second heterojunction and substantially without being connected to said first heterojunction; and a third control electrode including said second semiconductor layer as a contact region for applying an electric field to said third semiconductor layer so as to effect in controlling flow of induced tunneling current of said first and second carriers between said first and second heterojunctions in accordance with the electric field in said third semiconductor layer.

Claim 15

A high-frequency and low-noise semiconductor transistor device comprising: first, second and third semiconductor layers vertically disposed in an arrangement wherein said third semiconductor layer is formed on said first semiconductor layer and said second semiconductor layer is formed on said third semiconductor layer, said third semiconductor layer having first carriers at a first heterojunction formed by said first and third semiconductor layers and second carriers at a second heterojunction formed by said second and third semiconductor layers and having a band gap narrower than those of said first and second semiconductor layers so that band discontinuities in conduction bands and valence bands of the three layers form barriers to said first and second carriers; a first electrode having a contact region disposed in a portion of said third semiconductor layer and extending to a main surface of said device so as to be electrically connected to said first heterojunction and substantially without being connected to said second heterojunction; a second electrode having a contact region disposed in a portion of said third semiconductor layer and extending to the main surface of said device so as to be substantially electrically connected to said second heterojunction and substantially without being connected to said first heterojunction; and a third control electrode including said second semiconductor layer as a contact region for applying an electric field to said third semiconductor layer so as to effect in controlling flow of induced tunneling current of said first and second carriers between said first and second heterojunctions in accordance with the electric field in said third semiconductor layer.

Claim 16

A semiconductor transistor device according to claim 13, wherein said first and second carriers are two-dimensional hole and electron gas layers, respectively.

Claim 17

A semiconductor transistor device according to claim 14, wherein said third semiconductor layer has a p + doped region and an n + doped region so as to form a p + /n + junction therein.

Claim 18

A semiconductor transistor device according to claim 14, wherein said third semiconductor layer is undoped, and said first and second semiconductor layers are p + and n + doped layers, respectively.

Claim 19

A semiconductor transistor device according to claim 16, wherein said first semiconductor layer is formed on a substrate.

Claim 20

A semiconductor transistor device according to claim 15, wherein said first semiconductor layer includes a buffer layer formed on a substrate.

Claim 21

A semiconductor transistor device according to claim 13, wherein said first semiconductor layer is a substrate.

Claim 22

A semiconductor transistor device according to claim 16, wherein said first semiconductor layer is made of a semiconductor material principally composed of GaAs, said second semiconductor layer is made of a semiconductor material principally composed of Al x Ga 1-x As, and said third semiconductor layer is made of a semiconductor material principally composed of Ge.

Claim 23

A semiconductor transistor device according to claim 19, wherein said first semiconductor layer is made of a semiconductor material principally composed of InP, said second semiconductor layer is made of a semiconductor material principally composed of In 0 .52 Al 0 .48 As, and said third semiconductor layer is made of a semiconductor material principally composed of In 0 .53 Ga 0 .47 As.

Claim 24

A semiconductor transistor device according to claim 19, wherein said first electrode contact region comprises one of a diffused Zn doped layer and an ion-implanted layer of Be, and wherein said second electrode contact region comprises an ion-implanted layer of Si.

Claim 25

A semiconductor transistor device according to claim 18, wherein said first electrode contact region comprises one of a diffused Zn doped layer and an ion-implanted layer of Be, and wherein said second electrode contact region comprises an ion-implanted layer of Si.

Claim 26

A semiconductor transistor device according to claim 20, wherein said first electrode contact region comprises one of a diffused Zn doped layer and an ion-implanted layer of Be, and wherein said second electrode contact region comprises an ion-implanted layer of Si.

Claim 27

A semiconductor transistor device according to claim 21, wherein said first electrode contact region comprises one of a diffused Zn doped layer and an ion-implanted layer of Be, and wherein said second electrode contact region comprises an ion-implanted layer of Si.

Claim 28

A semiconductor transistor device according to claim 13, wherein said first, second and third electrodes comprise drain, source and gate electrodes of a field-effect transistor device.