MOS voltage to current converter

Claim 2

A MOS circuit comprising: a first supply voltage terminal for receiving a first supply voltage; a second supply voltage terminal for receiving a second supply voltage; a third supply voltage terminal for receiving a conversion voltage; an output current sink terminal; an output current source terminal; voltage divider means coupled between said second and third supply voltage terminals, wherein the conversion voltage provides power for said circuit and may vary over a range extending from two thresholds voltage above the second supply voltage to a V be above the first supply voltage, said voltage divider means having a voltage reference node for providing a reference voltage relative to the conversion voltage; linear reference current generator means coupled to said first, second, and third supply voltage terminals, and coupled to said voltage reference node for providing a linear reference current whose magnitude varies linearly in response to a corresponding change in the conversion voltage; and output means coupled between said second and third supply voltage terminals and coupled to said linear reference current generator means for providing an output sink current and an output source current at said output current sink terminal and said output current source terminal, respectively, wherein the magnitude of the output sink current and the magnitude of the output source current are a ratio of the magnitude of the linear reference current.

Claim 3

A circuit according to claim 1 wherein said voltage divider means comprises: a first resistor coupled between said third supply voltage terminal and the voltage reference node; and a second resistor coupled between the voltage reference node and said second supply voltage terminal.

Claim 4

A circuit according to claim 1 wherein said linear reference current generator means comprises: a gain terminal; a gain resistor coupled between said gain terminal and said second supply voltage terminal; a first current mirror means coupled between said third supply voltage terminal and said gain terminal and coupled to the voltage reference node for generating the linear reference current wherein the value of said gain resistor in conjunction with the magnitude of the conversion voltage determines the magnitude of the linear reference current flowing in said first current mirror means; a second current mirror means coupled to said second supply voltage terminal and the voltage reference node for providing a feedback current to said first current mirror means; a first field effect transistor having a source coupled to said first supply voltage terminal and a gate and a drain coupled to said first current mirror means; a second field effect transistor having a gate coupled to said first current mirror means, a source coupled to said third supply voltage terminal, and having a drain; and a third field effect transistor having a source coupled to the drain of said second field effect transistor, a gate coupled to said gain terminal, and a drain coupled to said second current mirror means.

Claim 5

A circuit according to claim 3 wherein said output means comprises: a third current mirror means coupled between said second supply voltage terminal and said output current sink terminal for sinking a current from said output current sink terminal; a fourth field effect transistor having a source coupled to said third supply voltage terminal, a gate coupled to said linear reference current generator means, and having a drain; a fifth field effect transistor having a source and a gate coupled to the drain of said fourth field effect transistor and a drain coupled to said third current mirror means; and a sixth field effect transistor having a source coupled to said third supply voltage terminal, a gate coupled to the gate of said fourth field effect transistor, and a drain coupled to said output current source terminal.

Claim 6

A circuit according to claim 4 wherein said first current mirror means comprises: a seventh field effect transistor having a source coupled to said third supply voltage terminal, a gate coupled to the gate of said second field effect transistor, and a drain coupled to the gate and the drain of said first field effect transistor; an eighth field effect transistor having a source coupled to said third supply voltage terminal, and a gate and a drain coupled to the gate of said second field effect transistor; a ninth field effect transistor having a gate and a source coupled to the drain of said seventh field effect transistor, and a drain coupled to the voltage reference node; and a tenth field effect transistor having a drain coupled to the gate of said second field effect transistor, a gate coupled to the gate of said ninth field effect transistor, and a source coupled to said gain terminal.

Claim 7

A circuit according to claim 5 wherein said second current mirror means comprises: an eleventh field effect transistor having a gate and a drain coupled to the drain of said third field effect transistor, and a source coupled to said second supply voltage terminal; and a twelfth field effect transistor having a drain coupled to the voltage reference node, a gate coupled to the gate of said eleventh field effect transistor, and a source coupled to said second supply voltage terminal.

Claim 8

A circuit according to claim 6 wherein said third current mirror means comprises: a thirteenth field effect transistor having a gate and a drain coupled to the drain of said fifth field effect transistor, and a source coupled to said second supply voltage terminal; and a fourteenth field effect transistor having a drain coupled to said output current sink terminal, a gate coupled to the gate of said thirteenth field effect transistor, and a source coupled to said second supply voltage terminal.

Claim 9

A circuit comprising: a first supply voltage terminal; a second supply voltage terminal; a third supply voltage terminal; an output current sink terminal; an output current source terminal; a gain terminal; a first resistor coupled between said third supply voltage terminal and a voltage reference node; a second resistor coupled between the voltage reference node and said second supply voltage terminal; a first field effect transistor having a source coupled to said first supply voltage terminal, and having a gate and a drain; a second field effect transistor having a source coupled to said third supply voltage terminal, a gate coupled to a current reference node, and having a drain; a third field effect transistor having a source coupled to the drain of said second field effect transistor, a gate coupled to said gain terminal, and having a drain; a fourth field effect transistor having a source coupled to said third supply voltage terminal, a gate coupled to the current reference node, and having a drain; a fifth field effect transistor having a source and a gate coupled to the drain of said fourth field effect transistor, and having a drain; a sixth field effect transistor having a source coupled to said third supply voltage terminal, a gate coupled to the current reference node, and a drain coupled to said output current source terminal; a seventh field effect transistor having a source coupled to said third supply voltage terminal, a gate coupled to the current reference node, and a drain coupled to the gate and the drain of said first field effect transistor; an eighth field effect transistor having a source coupled to said third supply voltage terminal, and a gate and a drain coupled to the current reference node; a ninth field effect transistor having a source and a gate coupled to the drain of said seventh field effect transistor, and a drain coupled to the voltage reference node; a tenth field effect transistor having a drain coupled to the current reference node, a gate coupled to the gate of said ninth field effect transistor, and a source coupled to said gain terminal; a gain resistor coupled between said gain terminal and said second supply voltage terminal; an eleventh field effect transistor having a gate and a drain coupled to the drain of said third field effect transistor, and a source coupled to said second supply voltage terminal; a twelfth field effect transistor having a drain coupled to the voltage reference node, a gate coupled to the gate of said eleventh field effect transistor, and a source coupled to said second supply voltage terminal; a thirteenth field effect transistor having a gate and a drain coupled to the drain of said fifth field effect transistor, and a source coupled to said second supply voltage terminal; and a fourteenth field effect transistor having a drain coupled to said output current sink terminal, a gate coupled to the gate of said thirteenth field effect transistor, and a source coupled to said second supply voltage terminal.

Claim 10

A circuit comprising: a first supply voltage terminal; a second supply voltage terminal; a third supply voltage terminal; an output current sink terminal; an output current source terminal; a gain terminal; a first resistor coupled between said third supply voltage terminal and a voltage reference node; a second resistor coupled between the voltage reference node and said second supply voltage terminal; a first field effect transistor having a source coupled to said first supply voltage terminal, and having a gate and a drain; a second field effect transistor having a source coupled to said third supply voltage terminal, a gate coupled to a current reference node, and having a drain; a third field effect transistor having a source coupled to the drain of said second field effect transistor, a gate coupled to said gain terminal, and having a drain; a fourth field effect transistor having a source coupled to said third supply voltage terminal, a gate coupled to the current reference node, and having a drain; a fifth field effect transistor having a source and a gate coupled to the drain of said fourth field effect transistor, and having a drain; a sixth field effect transistor having a source coupled to said third supply voltage terminal, a gate coupled to the current reference node, and a drain coupled to said output current source terminal; a seventh field effect transistor having a source coupled to said third supply voltage terminal, a gate coupled to the current reference node, and a drain coupled to the gate and the drain of said first field effect transistor; an eighth field effect transistor having a source coupled to said third supply voltage terminal, and a gate and a drain coupled to the current reference node; a ninth field effect transistor having a source and a gate coupled to the drain of said seventh field effect transistor, and a drain coupled to the voltage reference node; a tenth field effect transistor having a drain coupled to the current reference node, a gate coupled to the gate of said ninth field effect transistor, and a source coupled to said gain terminal; a gain resistor coupled between said gain terminal and said second supply voltage terminal; an eleventh field effect transistor having a gate and a drain coupled to the drain of said third field effect transistor, and a source coupled to said second supply voltage terminal; a twelfth field effect transistor having a drain coupled to the voltage reference node, a gate coupled to the gate of said eleventh field effect transistor, and a source coupled to said second supply voltage terminal; a thirteenth field effect transistor having a gate and a drain coupled to the drain of said fifth field effect transistor, and a source coupled to said second supply voltage terminal; and a fourteenth field effect transistor having a drain coupled to said output current sink terminal, a gate coupled to the gate of said thirteenth field effect transistor, and a source coupled to said second supply voltage terminal.

Claim 11

A MOS circuit comprising: a first supply voltage terminal for receiving a first supply voltage; a second supply voltage terminal for receiving a second supply voltage; a third supply voltage terminal for receiving a conversion voltage; an output current sink terminal; an output current source terminal; voltage divider means coupled between said first and third supply voltage terminals, wherein the conversion voltage provides power for said circuit and may vary over a range extending from two threshold voltages below the first supply voltage to a V be below the second supply voltage, said voltage divider means having a voltage reference node for providing a reference voltage relative to a conversion voltage; linear reference current generator means coupled to said first, second, and third supply voltage terminals, and coupled to said voltage reference node for providing a linear reference current whose magnitude varies linearly in response to a corresponding change in the conversion voltage; and output means coupled between said first and third supply voltage terminals and coupled to said linear reference current generator means for providing an output sink current and an output source current at said output current sink terminal and said output current source terminal, respectively, wherein the magnitude of the output sink current and the magnitude of the output source current are a ratio of the magnitude of the linear reference current.

Claim 12

A MOS circuit comprising: a first supply voltage terminal for receiving a first supply voltage; a second supply voltage terminal for receiving a second supply voltage; a third supply voltage terminal for receiving a conversion voltage; an output current sink terminal; an output current source terminal; voltage divider means coupled between said first and third supply voltage terminals, wherein the conversion voltage provides power for said circuit and may vary over a range extending from two threshold voltages below the first supply voltage to a V be below the second supply voltage, said voltage divider means having a voltage reference node for providing a reference voltage relative to a conversion voltage; linear reference current generator means coupled to said first, second, and third supply voltage terminals, and coupled to said voltage reference node for providing a linear reference current whose magnitude varies linearly in response to a corresponding change in the conversion voltage; and output means coupled between said first and third supply voltage terminals and coupled to said linear reference current generator means for providing an output sink current and an output source current at said output current sink terminal and said output current source terminal, respectively, wherein the magnitude of the output sink current and the magnitude of the output source current are a ratio of the magnitude of the linear reference current.

Claim 13

A circuit according to claim 9 wherein said voltage divider means comprises: a first resistor coupled between said first supply voltage terminal and the voltage reference node; and a second resistor coupled between the voltage reference node and said third supply voltage terminal

Claim 14

A circuit according to claim 9 wherein said linear reference current generator means comprises: a gain terminal; a gain resistor coupled between said gain terminal and said second supply voltage terminal; a first current mirror means coupled between said first supply voltage terminal and said gain terminal and coupled to the voltage reference node for generating the linear reference current wherein the value of said gain resistor in conjunction with the magnitude of the conversion voltage determines the magnitude of the linear reference current flowing in said first current mirror means; a second current mirror means coupled to said third supply voltage terminal and the voltage reference node for providing a feedback current to said first current mirror means; a first field effect transistor having a source coupled to said first supply voltage terminal and a gate and a drain coupled to said first current mirror means; a second field effect transistor having a gate coupled to said first current mirror means, a source coupled to said first supply voltage terminal, and having a drain; and a third field effect transistor having a source coupled to the drain of said second field effect transistor, a gate coupled to said gain terminal, and a drain coupled to said second current mirror means.

Claim 15

A circuit according to claim 11 wherein said output means comprises: a third current mirror means coupled between said third supply voltage terminal and said output current sink terminal for sinking a current from said output current sink terminal; a fourth field effect transistor having a source coupled to said first supply voltage terminal, a gate coupled to said linear reference current generator means, and having a drain; a fifth field effect transistor having a source and a gate coupled to the drain of said fourth field effect transistor and a drain coupled to said third current mirror means; and a sixth field effect transistor having a source coupled to said first supply voltage terminal, a gate coupled to the gate of said fourth field effect transistor, and a drain coupled to said output current source terminal.

Claim 16

A circuit according to claim 12 wherein said first current mirror means comprises: a seventh field effect transistor having a source coupled to said first supply voltage terminal, a gate coupled to the gate of said second field effect transistor, and a drain coupled to the gate and the drain of said first field effect transistor; an eighth field effect transistor having a source coupled to said first supply voltage terminal, and a gate and a drain coupled to the gate of said second field effect transistor; a ninth field effect transistor having a gate and a source coupled to the drain of said seventh field effect transistor, and a drain coupled to the voltage reference node; and a tenth field effect transistor having a drain coupled to the gate of said second field effect transistor, a gate coupled to the gate of said ninth field effect transistor, and a source coupled to said gain terminal.

Claim 17

A circuit according to claim 13 wherein said second current mirror means comprises: an eleventh field effect transistor having a gate and a drain coupled to the drain of said third field effect transistor, and a source coupled to said third supply voltage terminal; and a twelfth field effect transistor having a drain coupled to the voltage reference node, a gate coupled to the gate of said eleventh field effect transistor, and a source coupled to said third supply voltage terminal

Claim 18

A circuit according to claim 14 wherein said third current mirror means comprises: a thirteenth field effect transistor having a gate and a drain coupled to the drain of said fifth field effect transistor, and a source coupled to said third supply voltage terminal; and a fourteenth field effect transistor having a drain coupled to said output current sink terminal, a gate coupled to the gate of said thirteenth field effect transistor, and a source coupled to said third supply voltage terminal.

Claim 19

A circuit comprising: a first supply voltage terminal; a second supply voltage terminal; a third supply voltage terminal; an output current sink terminal; an output current source terminal; a gain terminal; a first resistor coupled between said first supply voltage terminal and a voltage reference node; a second resistor coupled between the voltage reference node and said third supply voltage terminal; a first field effect transistor having a source coupled to said first supply voltage terminal, and having a gate and a drain; a second field effect transistor having a source coupled to said first supply voltage terminal, a gate coupled to a current reference node, and having a drain; a third field effect transistor having a source coupled to the drain of said second field effect transistor, a gate coupled to said gain terminal, and having a drain; a fourth field effect transistor having a source coupled to said first supply voltage terminal, a gate coupled to the current reference node, and having a drain; a fifth field effect transistor having a source and a gate coupled to the drain of said fourth field effect transistor, and having a drain; a sixth field effect transistor having a source coupled to said first supply voltage terminal, a gate coupled to the current reference node, and a drain coupled to said output current source terminal; a seventh field effect transistor having a source coupled to said first supply voltage terminal, a gate coupled to the current reference node, and a drain coupled to the gate and the drain of said first field effect transistor; an eighth field effect transistor having a source coupled to said first supply voltage terminal, and a gate and a drain coupled to the current reference node; a ninth field effect transistor having a source and a gate coupled to the drain of said seventh field effect transistor, and a drain coupled to the voltage reference node; a tenth field effect transistor having a drain coupled to the current reference node, a gate coupled to the gate of said ninth field effect transistor, and a source coupled to said gain terminal; a gain resistor coupled between said gain terminal and said second supply voltage terminal; an eleventh field effect transistor having a gate and a drain coupled to the drain of said third field effect transistor, and a source coupled to said third supply voltage terminal; a twelfth field effect transistor having a drain coupled to the voltage reference node, a gate coupled to the gate of said eleventh field effect transistor, and a source coupled to said third supply voltage terminal; a thirteenth field effect transistor having a gate and a drain coupled to the drain of said fifth field effect transistor, and a source coupled to said third supply voltage terminal; and a fourteenth field effect transistor having a drain coupled to said output current sink terminal, a gate coupled to the gate of said thirteenth field effect transistor, and a source coupled to said third supply voltage terminal.

Claim 20

A circuit comprising: a first supply voltage terminal; a second supply voltage terminal; a third supply voltage terminal; an output current sink terminal; an output current source terminal; a gain terminal; a first resistor coupled between said first supply voltage terminal and a voltage reference node; a second resistor coupled between the voltage reference node and said third supply voltage terminal; a first field effect transistor having a source coupled to said first supply voltage terminal, and having a gate and a drain; a second field effect transistor having a source coupled to said first supply voltage terminal, a gate coupled to a current reference node, and having a drain; a third field effect transistor having a source coupled to the drain of said second field effect transistor, a gate coupled to said gain terminal, and having a drain; a fourth field effect transistor having a source coupled to said first supply voltage terminal, a gate coupled to the current reference node, and having a drain; a fifth field effect transistor having a source and a gate coupled to the drain of said fourth field effect transistor, and having a drain; a sixth field effect transistor having a source coupled to said first supply voltage terminal, a gate coupled to the current reference node, and a drain coupled to said output current source terminal; a seventh field effect transistor having a source coupled to said first supply voltage terminal, a gate coupled to the current reference node, and a drain coupled to the gate and the drain of said first field effect transistor; an eighth field effect transistor having a source coupled to said first supply voltage terminal, and a gate and a drain coupled to the current reference node; a ninth field effect transistor having a source and a gate coupled to the drain of said seventh field effect transistor, and a drain coupled to the voltage reference node; a tenth field effect transistor having a drain coupled to the current reference node, a gate coupled to the gate of said ninth field effect transistor, and a source coupled to said gain terminal; a gain resistor coupled between said gain terminal and said second supply voltage terminal; an eleventh field effect transistor having a gate and a drain coupled to the drain of said third field effect transistor, and a source coupled to said third supply voltage terminal; a twelfth field effect transistor having a drain coupled to the voltage reference node, a gate coupled to the gate of said eleventh field effect transistor, and a source coupled to said third supply voltage terminal; a thirteenth field effect transistor having a gate and a drain coupled to the drain of said fifth field effect transistor, and a source coupled to said third supply voltage terminal; and a fourteenth field effect transistor having a drain coupled to said output current sink terminal, a gate coupled to the gate of said thirteenth field effect transistor, and a source coupled to said third supply voltage terminal.