Line equalizer

Claim 1

A line equalizer comprising: an input terminal (1) to which a pulse signal having a transmission fundamental period of T is inputted; a delay element (2), connected with said input terminal, for delaying said input pulse signal by a period of T; a coefficient multiplier (4), connected with said input terminal, for multiplying said input pulse signal by a coefficient a; an adder (3-1) for addng an output from said delay element and an output from said multiplier; and a decision circuit (8) for deciding an output pulse signal from said adder for each period T which includes a first comparator (8-1) for generating a first pulse signal when said output pulse signal exceeds a positive predetermined value, a second comparator (8-2) for generating a second pulse signal when said output pulse exceeds a negative predetermined value, a first logic element (8-3) for generating a third pulse signal when both of said first and second pulse signals are generated, a second logic element (8-4) for generating a fourth pulse signal when both of said first and second pulse signals are not generated, and a third logic element (8-5) for generating a fifth pulse signal obtained by a combination of said third and fourth pulse signals to an output terminal; an error signal decision circuit (3-2) for generating a residual equalizing error on the basis of said third and fourth pulse signals and the output pulse signal from said adder; a first control circuit (9) for sending a postcursor signal to said adder on the basis of said third and fourth pulse signals and said residual equalizing error; and a second control circuit (10) for changing the coefficient a of said multiplier on the basis of a signal obtained by delaying said residual equalizing error by the period T and said third and fourth pulse signals, wherein said delay element (2), said coefficient multiplier (4) and said adder (3-1) constitute a precursor equalizer and said adder (3-1) and said first control circuit (9) constitute a postcursor equalizer.