Data transmission system between a main CPU board having a wait signal generating latch and a plurality of CPU boards

Claim 1

A data transmission system between a plurality of CPU's in a key telephone system comprising: a main board on which a main CPU and a latch circuit are installed; a plurality of sub-boards, each of said sub-boards having both a gate circuit and a sub-CPU installed thereon, whereby said gate circuit is connected between said sub-CPU and said main board latch circuit by a wait clear line, such that said latch circuit provides a wait signal to said main CPU upon a read or write of said main CPU with respect to said sub-CPU and said wait clear line provides to said latch circuit a wait clear signal, indicative of completion of input and output of said sub-CPU, to release a waited state of said main CPU; said latch circuit further comprising means which generates said wait clear signal independently of said sub-CPU's on said plurality of sub-boards after a predetermined time interval from address setting of said main CPU for the sub-CPU's for releasing said wait of said main CPU, said releasing means including at least a one-shot multivibrator which varies its output level after a predetermined time interval from a receipt of a wait set signal; a data bus connected between said main CPU of said main board and said sub-CPU's of said plurality of sub-boards; and, a CPU select line connected to said sub-CPU's for sending a CPU select signal from said main CPU to a selected one of said sub-CPU's; wherein data and command transmission is performed through said read or write of said main CPU.