Data processing system including a separate input/output processor with micro-interrupt request apparatus

Claim 2

A data processing system comprising a host processor having a microprogram control store, a host processor memory, and a host memory management unit, the contents of which permit the conversion of logical addresses received by said host processor into physical addresses for said host memory, and further comprising an input/output processor; input/output bus means for providing communication between said input/output processor and said host processor, said host processor being capable of generating a specified coded signal in response to any interrupt request from said input/output processor; said input/output processor including means for generating a micro-interrupt request signal for said host processor to request a re-allocation of a selected position of the contents of said memory management unit; and micro-interrupt indentifying means responsive to said specified coded signal received from said host processor and to said micro-interrupt request signal of said input/output processor for providing a signal to said host processor for identifying said interrupt request as one requiring the re-allocation of said selected portion of the contents of said memory management unit, whereby said host processor can perform such re-allocation in accordance with a specified program in its micro-program control store; said input/out processor thereby being capable of accessing said host memory and said memory management unit via said input/output bus means for the direct transfer of logical addresses to said re-allocated selected portion of said memory management unit and for the direct transfer of data between said input/output processor and said host memory when said selected portion of said memory management unit has been re-allocated.

Claim 3

A data processing system in accordance with claim 1 wherein said input/output processor has an instruction register containing an instruction and said micro-interrupt identifying means includes first logic means responsive to a first fixed coded signal and to a coded portion of said instruction signal from said instruction register for providing a first matching signal when said first fixed coded signal and said coded portion of said instruction signal match; and second logic means responsive to said first signal and to said micro-interrupt request signal for providing a second signal indicating that a micro-interrupt has been requested.

Claim 4

A data processing system in accordance with claim 2 wherein said micro-interrupt identifying means further includes second means responsive to a second fixed coded signal and to said specified coded signal from said host processor to provide a second matching signal when said second fixed coded signal and said specified coded signal match; means responsive to said second signal and and to a periodic signal from said host processor to provide an internal interrupt signal; means responsive to said second matching signal and to said internal interrupt signal for providing an external condition signal to said host processor indicating that the interrupt request is a true micro-interrupt request.

Claim 5

A data processing system in accordance with claim 3 wherein said input/output processor further includes means responsive to a signal provided by said host processor when the re-allocation of said selected portion of said memory management unit has been completed for providing a signal to the input/output processor control logic means to indicate that said re-allocation has been completed.

Claim 6

A data processing system in accordance with claim 1 wherein said input/output processor has a local memory and further includes window map means for selectively providing access to said local memory or to said host processor memory in accordance with a selected memory reference signal, said window map means comprising multiplexer means capable of being responsive to either a program memory reference signal or a data channel memory reference signal and further responsive to a memory reference identifying signal which selects which of said memory reference signals the multiplexer means is responsive to, said multiplexer means thereby selectively providing an enabling signal which depends on the state of the memory reference signal to which said multiplexer means responds; and inhibit logic means responsive to the selective provision of said enabling signal and to said memory reference identifying signal for inhibiting access either to said local memory or to said host processor memory depending on whether the memory reference is to said local memory or to said host processor memory.

Claim 7

A data processing system in accordance with claim 5 wherein said inhibit logic means includes means for providing a first inhibit signal for inhibiting the start of the interface of said input/output processor and said local memory when the memory reference to to said host processor memory and means for providing a second inhibit signal for inhibiting the start of the interface of said input/output processor and said host processor when the memory reference is to said local memory.

Claim 8

A data processing system in accordance with claim 6 wherein said host memory management unit has a plurality of memory allocation units and said multiplexer means is further responsive to a selected one of two sets of bits depending on whether the memory reference is a program memory reference or a data channel memory reference for providing an output set of bits for identifying a selected one of said plurality of memory allocation units, said output set of bits being supplied to said host processor as an extension of the logical address for said memory reference.

Claim 9

A data processing system in accordance with claim 7 wherein each of said two sets of bits comprises a pair of bits and said output set of bits is a pair of bits for identifying one of four of said plurality of memory allocation units.

Claim 10

A data processing system in accordance with claim 1 wherein said input/output processor further includes means for preventing any other processor from accessing said host processor memory when said input/output processor is performing a read-modify-write operation with respect to data in said host processor memory.

Claim 11

A data processing system in accordance with claim 9 wherein said access preventing means includes means for generating an access inhibiting signal which starts when the data in said host processor memory is being read by said input/output processor and ends when the modified data is being rewritten into said host processor memory, said access inhibiting signal being supplied to other input/output processors on the host input/output bus means to prevent other processors from obtaining access to the location in said host memory at which said data is being read, modified and rewritten.

Claim 12

A data processing system comprising a host processor having a microprogram control store, a host memory and a host memory management unit and further comprising an input/output processor; first input/output bus means for providing communication between said input/output processor and host processor; second input/output bus means for providing communication between said input/output processor and one or more devices external to said input/output processor; said input/output processor including a local memory; a logical address bus in said input/output processor for providing logical addresses for said local memory or said host memory; and window map means connected to said logical address bus for selectively providing access by said input/output processor or by said one or more external devices to said local memory or to said host processor memory in accordance with a selected memory reference signal, said window map means comprising multiplexer means capable of being responsive to either a user mode signal generated by said input/output processor or a data channel mode signal generated by said input/output processor and further responsive to a memory reference identifying signal generated by said input/output processor which selects which of said user mode or data channel mode signals the multiplexer means is responsive to, said multiplexer means thereby selectively providing a window map enabling signal which depends on the state of the selected user mode or data channel mode signal to which said multiplexer means responds; and inhibit logic means comprising random access memory means responsive to said window map enabling signal, to said memory reference identifying signal and to address bits from said logical address bus for inhibiting access by said input/output processor or by said one or more external devices either to said local memory or to said host processor memory depending on the contents of said random access memory means.

Claim 13

A data processing system comprising a host processor having a microprogram control store, a host memory and a host memory management unit and further comprising an input/output processor; first input/output bus means for providing communication between said input/output processor and host processor; second input/output bus means for providing communication between said input/output processor and one or more devices external to said input/output processor; said input/output processor including a local memory; a logical address bus in said input/output processor for providing logical addresses for said local memory or said host memory; and window map means connected to said logical address bus for selectively providing access by said input/output processor or by said one or more external devices to said local memory or to said host processor memory in accordance with a selected memory reference signal, said window map means comprising multiplexer means capable of being responsive to either a user mode signal generated by said input/output processor or a data channel mode signal generated by said input/output processor and further responsive to a memory reference identifying signal generated by said input/output processor which selects which of said user mode or data channel mode signals the multiplexer means is responsive to, said multiplexer means thereby selectively providing a window map enabling signal which depends on the state of the selected user mode or data channel mode signal to which said multiplexer means responds; and inhibit logic means comprising random access memory means responsive to said window map enabling signal, to said memory reference identifying signal and to address bits from said logical address bus for inhibiting access by said input/output processor or by said one or more external devices either to said local memory or to said host processor memory depending on the contents of said random access memory means.

Claim 14

A data processing system in accordance with claim 11 wherein said inhibit logic means includes means for providing a first inhibit signal for inhibiting the start of the interface of said input/output processor and said local memory when the memory reference is to said host processor memory and means for providing a second inhibit signal for inhibiting the start of the interface of said input/output processor and said host processor when the memory reference is to said local memory.

Claim 15

A data processing system in accordance with claim 12 wherein said memory management unit has a plurality of memory allocation units and said multiplexer means is further responsive to a selected one of two sets of bits depending on whether the memory reference is a program memory reference or a data channel memory reference for providing an output set of bits for identifying a selected one of said plurality of memory allocation units, said output set of bits being supplied to said host processor as an extension of the logical address for said memory reference.