Merged multi-collector transistor

Claim 2

A merged lateral PNP transistor, comprising: a plurality of collectors; a common base; a plurality of emitters, each emitter having a predetermined number of collectors in spaced relationship thereto and each one of said plurality of emitters being in spaced relationship to an adjacent one of said plurality of emitters wherein certain ones of said predetermined number of said collectors are merged with certain other ones of said predetermined number of collectors associated with each adjacent emitter; and conductive means for interconnecting particular ones of said plurality of colletors associated with different ones of said plurality of emitters including predetermined ones of said plurality of emitters that are not adjacent to one another to provide a plurality of collector outputs from the transistor whereby any errors associated with the collector outputs are averaged thereby reducing such errors.

Claim 3

The lateral PNP transistor of claim 1 wherein said plurality of emitters each have substantially equal areas, said plurality of emitters being aligned in two rows adjacent to one another.

Claim 4

The lateral PNP transistor of claim 2 wherein each emitter is rectangular in shape and includes four collectors of said plurality of collectors spaced equidistant about the four sides of the rectangle forming said emitter.

Claim 5

The lateral PNP transistor of claim 3 wherein said plurality of emitters includes twenty-four emitters formed in two rows of twelve emitters each substantially equidistant apart with each emitter in one of said two rows being spaced directly across from a corresponding emitter forming the second row.

Claim 6

A merged multi-collector PNP transistor having a substrate, comprising: a base epitaxial region formed on the substrate; a plurality of emitter regions disposed in said base epitaxial region in at least first and second rows, each one of said plurality of emitter regions being adjacent to at least one other one of said plurality of emitter regions in said first and second rows; a plurality of collector regions disposed in said base epitaxial region, a predetermined number of said plurality of collectors being associated about a particular one of each of said plurality of emitter regions with adjacent emitter regions in said at least first and second rows having said collector regions formed therebetween merged into one structure; and conductive means for interconnecting particular ones of said plurality of collector regions associated with different ones of said plurality of emitter regions of said at least first and second rows including predetermined ones of said plurality of emitter regions that are not adjacent to one another to provide a plurality of collector outputs from the transistor whereby any errors associated with the collector regions are averaged thereby reducing such errors.

Claim 7

A merged multi-collector PNP transistor having a substrate, comprising: a base epitaxial region formed on the substrate; a plurality of emitter regions disposed in said base epitaxial region in at least first and second rows, each one of said plurality of emitter regions being adjacent to at least one other one of said plurality of emitter regions in said first and second rows; a plurality of collector regions disposed in said base epitaxial region, a predetermined number of said plurality of collectors being associated about a particular one of each of said plurality of emitter regions with adjacent emitter regions in said at least first and second rows having said collector regions formed therebetween merged into one structure; and conductive means for interconnecting particular ones of said plurality of collector regions associated with different ones of said plurality of emitter regions of said at least first and second rows including predetermined ones of said plurality of emitter regions that are not adjacent to one another to provide a plurality of collector outputs from the transistor whereby any errors associated with the collector regions are averaged thereby reducing such errors.

Claim 8

An integrated current source circuit, comprising: a merged multi-collector PNP transistor formed laterally within the integrated circuit, said PNP transistor including a common base region, a plurality of emitter regions formed in said common base region in first and second rows with each emitter region being spaced substantially equidistance from an adjacent emitter region, each emitter region in one row being adjacent to a corresponding region in the other row, and plurality of collector regions formed in said common base region in spaced relationship to each other with each one of said plurality of emitter regions having a predetermined number of collector regions spaced thereabout with the collector regions associated between adjacent emitter regions of said first and second rows being merged together; means for coupling said plurality of emitter regions to an operating potential; conductive means for interconnecting predetermined ones of said collector regions associated with different ones of said emitter regions in said first and second rows; and circuit means coupled to said common base region for sourcing base current drive therefrom to render said merged multi-collector transistor conductive to produce a plurality of weighted currents at a plurality of outputs.

Claim 9

An integrated current source circuit, comprising: a merged multi-collector PNP transistor formed laterally within the integrated circuit, said PNP transistor including a common base region, a plurality of emitter regions formed in said common base region in first and second rows with each emitter region being spaced substantially equidistance from an adjacent emitter region, each emitter region in one row being adjacent to a corresponding region in the other row, and plurality of collector regions formed in said common base region in spaced relationship to each other with each one of said plurality of emitter regions having a predetermined number of collector regions spaced thereabout with the collector regions associated between adjacent emitter regions of said first and second rows being merged together; means for coupling said plurality of emitter regions to an operating potential; conductive means for interconnecting predetermined ones of said collector regions associated with different ones of said emitter regions in said first and second rows; and circuit means coupled to said common base region for sourcing base current drive therefrom to render said merged multi-collector transistor conductive to produce a plurality of weighted currents at a plurality of outputs.

Claim 10

The current source of claim 6 wherein each emitter region is rectangular in shape and has equal areas, each side of said rectangular emitter region having a collector region spaced therefrom.

Claim 11

The current source of claim 7 wherein said transistor includes twenty-four emitter regions and ninety-six collector regions.