Trench capacitor process for high density dynamic ram

Claim 1

A method of making a memory cell at a face of a semiconductor body, comprising the steps of: applying an oxidation mask to said face patterned to expose a bit line area and a capacitor area, implant an impurity into said face in said bit line area and said capacitor area to produce heavily doped areas, said implanting being masked by said oxidation mask, masking said face to expose only a part of said capacitor area of said face, etching said face in said part to create a trench which is deeper than its width, said etching including a first etching step to a depth just below said heavily doped area, followed by a step of growing thermal oxide inset into said heavily doped area and encircling the trench, then a second etching step to the remainder of the depth of the trench, growing a thick thermal oxide on said face in said bit line area and said capacitor area, said implanted impurity creating heavily doped regions beneath said thermal oxide, said thermal oxide growing much thinner in said trench than over said heavily doped areas, applying a conductive layer over said face and extending into said trench, said conductive layer being insulated from the body by an insulator coating, opening a hole in said conductive layer in a channel area between said bit line and said capacitor area, and depositing a conductor on said face and patterning the conductor to leave a transistor gate in said hole and a word line extending along said face perpendicular to said bit line.

Claim 2

A method of making a memory cell at a face of a semiconductor body, comprising the steps of: applying an oxidation mask to said face patterned to expose a bit line area and a capacitor area, implant an impurity into said face in said bit line area and said capacitor area to produce heavily doped areas, said implanting being masked by said oxidation mask, masking said face to expose only a part of said capacitor area of said face, etching said face in said part to create a trench which is deeper than its width, said etching including a first etching step to a depth just below said heavily doped area, followed by a step of growing thermal oxide inset into said heavily doped area and encircling the trench, then a second etching step to the remainder of the depth of the trench, growing a thick thermal oxide on said face in said bit line area and said capacitor area, said implanted impurity creating heavily doped regions beneath said thermal oxide, said thermal oxide growing much thinner in said trench than over said heavily doped areas, applying a conductive layer over said face and extending into said trench, said conductive layer being insulated from the body by an insulator coating, opening a hole in said conductive layer in a channel area between said bit line and said capacitor area, and depositing a conductor on said face and patterning the conductor to leave a transistor gate in said hole and a word line extending along said face perpendicular to said bit line.