Patent US4830972A successfully refreshed from Google Patents.
US4830972A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing bipolar transistor
Assignee: Toshiba Corp
•
Filing: 1988-02-04
•
Granted: 1989-05-16
•
Expires: 2008-02-04
Abstract
Abstract A method of manufacturing an ultra-miniaturized bipolar transistor is disclosed, wherein an insulating film and a first polysilicon film doped with an impurity of a second conductivity type are formed, in this order, as a collector on a semiconductor layer of a first conductivity type. After an opening is formed in a predetermined portion of the first polysilicon film, the insulating film is etched, using the first polysilicon film as a mask, to expose part of a surface of the substrate. Thereafter, an undoped second polysilicon film is deposited on the resultant structure, and is annealed without etching. Then, the impurity doped in the first polysilicon film is diffused into part of the second polysilicon film and simultaneously into the substrate to form an external base region of a second conductivity type. The second polysilicon film is etched by use of an etching method wherein the etching rate in an undoped region is much higher than that in an impurity-doped region. As a result, the undoped region can be selectively removed without using a mask, thereby exposing the substrate surface. Subsequently, an oxide film is formed on the polysilicon film and the substrate surface, and an impurity is doped through the opening to form an internal base layer. Thereafter, an emitter layer is formed, in a self-aligned manner, in the internal base region.
Inventors
- 👤 Toshihiko Hamasaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:36
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/051; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113; Y; Y10; Y10S; Y10S438/00; Y10S438/981
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
203 words
A method of manufacturing a bipolar transistor, comprising the steps of: depositing an impurity-doped first polysilicon film on a semiconductor layer of a first conductivity type, with an insulating film being interposed therebetween; forming an opening by selectively etching said first polysilicon film and selectively etching said insulating film, using a left portion of said first polysilicon film as a mask; forming an external base region of a second conductivity type by depositing an undoped second polysilicon film and annealing the resultant structure, to diffuse an impurity contained in said first polysilicon film into part of said second polysilicon film and into part of said substrate; selectively etching said second polysilicon film, without using a mask, by employing an etching method wherein an etching rate of an undoped region is higher than that of an impurity-doped region; forming thick and thin oxide films on surfaces of said impurity-doped polysilicon layer and said substrate, respectively, by thermally oxidizing said left impurity-doped polysilicon layer and the exposed surface of said substrate; and forming an internal base region, which is connected to said external base region, in the surface layer of said substrate at said opening, and forming an emitter region in said internal base region.
Claim 2
Independent Claim
203 words
A method of manufacturing a bipolar transistor, comprising the steps of: depositing an impurity-doped first polysilicon film on a semiconductor layer of a first conductivity type, with an insulating film being interposed therebetween; forming an opening by selectively etching said first polysilicon film and selectively etching said insulating film, using a left portion of said first polysilicon film as a mask; forming an external base region of a second conductivity type by depositing an undoped second polysilicon film and annealing the resultant structure, to diffuse an impurity contained in said first polysilicon film into part of said second polysilicon film and into part of said substrate; selectively etching said second polysilicon film, without using a mask, by employing an etching method wherein an etching rate of an undoped region is higher than that of an impurity-doped region; forming thick and thin oxide films on surfaces of said impurity-doped polysilicon layer and said substrate, respectively, by thermally oxidizing said left impurity-doped polysilicon layer and the exposed surface of said substrate; and forming an internal base region, which is connected to said external base region, in the surface layer of said substrate at said opening, and forming an emitter region in said internal base region.
Claim 3
Dependent Claim
38 words
A method according to claim 1, wherein the step of selectively etching said insulating film, using said first polysilicon film in which said opening is formed as a mask, is performed so as not to form undercut portions.
Claim 4
Dependent Claim
31 words
A method according to to claim 1, wherein said semiconductor substrate comprises a silicon substrate, and said insulating film comprises a stacked layer composed of silicon oxide and silicon nitride films.
Claim 5
Dependent Claim
16 words
A method according to claim 1, wherein said insulating film is constituted by a single layer.
Claim 6
Dependent Claim
30 words
A method according to claim 1, wherein the step of selectively etching said undoped region in said second polysilicon film is performed by wet etching, using an etchant containing hydrazine.
Claim 7
Independent Claim
221 words
A method of manufacturing a bipolar transistor, comprising the steps of: depositing an impurity-doped first polysilicon film on a semiconductor layer of a first conductivity type, with an insulating film being interposed therebetween; forming an opening by selectively etching said first polysilicon film and selectively etching said insulating film, using a left portion of said first polysilicon film as a mask so as to form undercut portions; forming an external base region of a second conductivity type by depositing an undoped second polysilicon film and annealing the resultant structure, to diffuse an impurity contained in said first polysilicon film into part of said second polysilicon film and into part of said substrate; selectively etching said second polysilicon film, without using a mask, by employing an etching method wherein an etching speed of an undoped region is higher than that of an impurity-doped region, and burying said second polysilicon film as an impurity-doped layer in said undercut portions; forming thick and thin oxide films on surfaces of said impurity-doped polysilicon layer and said substrate, respectively, by thermally oxidizing said surfaces of said impurity-doped polysilicon layer and said substrate; and forming an internal base region, which is connected to said external base region, in the surface layer of said substrate at said opening, and forming an emitter region in said internal base region.
Claim 8
Independent Claim
221 words
A method of manufacturing a bipolar transistor, comprising the steps of: depositing an impurity-doped first polysilicon film on a semiconductor layer of a first conductivity type, with an insulating film being interposed therebetween; forming an opening by selectively etching said first polysilicon film and selectively etching said insulating film, using a left portion of said first polysilicon film as a mask so as to form undercut portions; forming an external base region of a second conductivity type by depositing an undoped second polysilicon film and annealing the resultant structure, to diffuse an impurity contained in said first polysilicon film into part of said second polysilicon film and into part of said substrate; selectively etching said second polysilicon film, without using a mask, by employing an etching method wherein an etching speed of an undoped region is higher than that of an impurity-doped region, and burying said second polysilicon film as an impurity-doped layer in said undercut portions; forming thick and thin oxide films on surfaces of said impurity-doped polysilicon layer and said substrate, respectively, by thermally oxidizing said surfaces of said impurity-doped polysilicon layer and said substrate; and forming an internal base region, which is connected to said external base region, in the surface layer of said substrate at said opening, and forming an emitter region in said internal base region.
Claim 9
Dependent Claim
29 words
A method according to claim 6, wherein said first polysilicon film is oxidized after said first polysilicon film is selectively etched and before said insulating film is selectively etched.
Claim 10
Dependent Claim
31 words
A method according to claim 6, wherein said semiconductor substrate comprises a silicon substrate, and said insulating film comprises a stacked layer composed of said silicon oxide and silicon nitride films.
Claim 11
Dependent Claim
16 words
A method according to claim 6, wherein said insulating film is constituted by a single layer.
Claim 12
Dependent Claim
30 words
A method according to claim 6, wherein the step of selectively etching said undoped region in said second polysilicon film is performed by wet etching, using an etchant containing hydrazine.
References Cited (Backward Citations)
US4531282A
Cited
JPS5732511A
Cited
US4463493A
Cited
US4717689A
Cited
US4571817A
Cited
US4780427A
Cited
US4746629A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-15 | 1992-11-14 | 1993-05-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-15 | 1996-11-14 | 1997-05-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-15 | 2000-11-14 | 2001-05-16 | $7700.00 | Window Closed / Lapsed |