Process for making indium gallium arsenide devices

Claim 2

A semiconductor device comprising at least one junction field effect transistor, said junction field effect transistor comprising: a. first epitaxial region comprising III-V semiconductor compound with n-type conductivity; b. second epitaxial region comprising III-V semiconductor compound with p-type conductivity and contacting at least a portion of the first epitaxial region said second epitaxial region having a length; c. source and drain electrodes, said source and drain electrodes contacting said first epitaxial region; d. gate electrode contacting said second epitaxial region and having a length; characterized in that 1. The gate electrode is positioned on the second epitaxial region so that it overhangs the second epitaxial region; 2.

Claim 3

The length of the gate electrode is less than or equal to the distance between source and drain electrodes; 3. The length of said second epitaxial region measured along its interface with said first epitaxial region is less than the length of the gate electrode; 4. The first epitaxial layer and the second epitaxial layer comprise III-V semiconductor compounds approximately lattice matched to indium phosphide; 5. The bottom of the plane of the metallization of the gate electrode is above the top of the planes of the metallizations of the and drain electrodes so that the gate electrode is a shadow mask in the deposition of metal for the source and drain electrodes; 6. The edge of the source electrode and the edge drain electrode closest to the gate electrode are symmetrically disposed about the gate electrode; 7. The first epitaxial layer is in contact with a substrate comprising indium phosphide; and 8. The first epitaxial region and the second epitaxial region comprise III-V semiconductor compound with composition that is lattice matched to indium phosphide and selected from the group consisting of InGaAs,

Claim 4

The length of the gate electrode is less than or equal to the distance between source and drain electrodes; 3. The length of said second epitaxial region measured along its interface with said first epitaxial region is less than the length of the gate electrode; 4. The first epitaxial layer and the second epitaxial layer comprise III-V semiconductor compounds approximately lattice matched to indium phosphide; 5. The bottom of the plane of the metallization of the gate electrode is above the top of the planes of the metallizations of the and drain electrodes so that the gate electrode is a shadow mask in the deposition of metal for the source and drain electrodes; 6. The edge of the source electrode and the edge drain electrode closest to the gate electrode are symmetrically disposed about the gate electrode; 7. The first epitaxial layer is in contact with a substrate comprising indium phosphide; and 8. The first epitaxial region and the second epitaxial region comprise III-V semiconductor compound with composition that is lattice matched to indium phosphide and selected from the group consisting of InGaAs,

Claim 5

InGaAsP, InGaAlAs and InP. 2. The semiconductor device of claim 1 in which the first epitaxial region and second epitaxial region comprise the same III-V compound semiconductor.

Claim 6

The semiconductor device of claim 2 in which the first epitaxial region comprises n-type InP and the second epitaxial region comprises p-type InP.

Claim 7

The semiconductor device of claim 3 in which the n-type InP is doped with an element selected from the group consisting of Sn, Si, S, and Te.

Claim 8

The semiconductor device of claim 4 in which the doping concentration ranges from 10 16 -10 17 atoms/cc.

Claim 9

The semiconductor device of claim 5 in which the doping concentration is from 8-9×10 16 atoms/cc.

Claim 10

The semiconductor device of claim 3 in which the p-type InP is doped with an element selected from the group consisting of Cd, Zn, Mg, and Pe.

Claim 11

The semiconductor device of claim 7 in which the doping concentration ranges from 10 18 -10 19 atoms/cc.

Claim 12

The semiconductor device of claim 2 in which the first epitaxial region is n-type InGaAs and the second epitaxial region is p-type InGaAs.

Claim 13

The semiconductor device of claim 9 in which the n-type InGaAs is doped with an element selected from the group consisting of Sn, Si, S, and Te.

Claim 14

The semiconductor device of claim 10 in which the doping concentration ranges from 10 16 -10 17 atoms/cc.

Claim 15

The semiconductor device of claim 11 in which the doping concentration ranges from 5-7×10 16 atoms/cc.

Claim 16

The semiconductor device of claim 9 in which the p-type InGaAs is doped with an element selected from the group consisting of Cd, Zn, Mg, and Be.

Claim 17

The semiconductor device of claim 13 in which the doping concentration ranges from 10 18 -10 19 atoms/cc.

Claim 18

The semiconductor device of claim 1 in which the first epitaxial region and second epitaxial region comprise different III-V semiconductor compounds.

Claim 19

The semiconductor device of claim 2 in which the first epitaxial layer is n-type InP and the second epitaxial layer is p-type InGaAs.

Claim 20

The semiconductor device of claim 16 in which the n-type InP is doped with an element selected from the group consisting of Sn, Si, S, and Te.

Claim 21

The semiconductor device of claim 17 in which the doping concentration ranges from 10 16 -10 17 atoms/cc.

Claim 22

The semiconductor device of claim 18 in which the doping concentration ranges from 8-9×10 16 atoms/cc.

Claim 23

The semiconductor device of claim 16 in which the p-type InGaAs is doped with an element selected from the group consisting of Cd, Zn, Mg, and Be.

Claim 24

The semiconductor device of claim 20 in which the doping concentration ranges from 10 18 -10 19 atoms/cc.

Claim 25

The semiconductor device of claim 1 in which the first epitaxial layer is n-type InGaAs and the second epitaxial layer is p-type InP.

Claim 26

The semiconductor device of claim 22 in which the n-type InGaAs is doped with an element selected from the group Sn, Si, S, and Te.

Claim 27

The semiconductor device of claim 23 in which the doping concentration ranges from 10 16 -10 17 atoms/cc.

Claim 28

The semiconductor device of claim 24 in which the doping concentration ranges from 5-7×10 16 atoms/cc.

Claim 29

The semiconductor device of claim 22 in which the p-type InP is doped with an element selected from the group consisting of Cd, Zn, Mg, and Be.

Claim 30

The semiconductor device of claim 26 in which the doping concentration ranges from 10 18 -10 19 atoms/cc.

Claim 31

The semiconductor device of claim 1 in which the gate electrode is electrically connected to a gate pad.

Claim 32

The semiconductor device of claim 28 in which there is an air bridge between gate electrode and gate pad.

Claim 33

The semiconductor device of claim 1 in which the source electrode and drain electrode are within 2 μm of the second epitaxial region.

Claim 34

The semiconductor device of claim 30 in which the source electrode and drain electrode are within 1.0 μm of the second epitaxial region.

Claim 35

The semiconductor device of claim 1 in which the length of the second epitaxial region is less than 5 μm.

Claim 36

The semiconductor device of claim 1 in which the overhang of the gate electrode over second epitaxial layer is between 0.3 and 1.0 μm.

Claim 37

The semiconductor device of claim 33 in which the overhang is between 0.3 and 0.5 μm.

Claim 38

The semiconductor device of claim 1 in which the thickness of the first epitaxial region is less than 1 μm.

Claim 39

The semiconductor device of claim 1 in which the thickness of the second epitaxial region is less than 1 μm.

Claim 40

The semiconductor device of claim 1 in which the first epitaxial layer is in contact with a buffer layer which is semi-insulating and lattice matched to InP, said buffer in contact with a substrate comprising InP.

Claim 41

The semiconductor device of claim 37 in which the buffer layer is semi-insulating InP.

Claim 42

The semiconductor device of claim 37 in which the buffer layer is semi-insulating InAlAs lattice matched to InP.

Claim 43

The semiconductor device of claim 1 in which a portion of the second epitaxial region in contact with the gate electrode is highly doped with p-type dopant with concentration in the range from 1.0-8.0×10 19 atoms/cm 3 .