Data processing apparatus

Claim 2

A data processing apparatus comprising: decoder means receiving a microinstruction to generate at least a first selection signal and a number-of-selection signal; first counter means receiving a timing signal and controlled by the first selection signal to generate a first register address signal updated at the timing signal; register means including a plurality of registers and receiving the first register address signal to select one of the registers designated by the register address signal; second counter means operating to count up in response to the timing signal; and means comparing the content of the second counter means with the number-of-selection signal for incrementing a program counter when the content of the second counter means becomes consistent with the number-of-selection signal.

Claim 3

An apparatus claimed in claim 1 wherein the decoder means further generate a second register address signal, and further including selection means receiving the first and second register address signals for outputting to the register means one of the first and second register address signals in response to the first selection signal.

Claim 4

An apparatus claimed in claim 2 wherein the decoder means further generates a second selection signal to the second counter means, and wherein the second counter means is conditioned for counting in response to the timing signal while the second selection signal is active, and is also reset by the comparator means when the content of the second counter means becomes consistent with the number-of-selection signal.

Claim 5

An apparatus claimed in claim 3 wherein the first counter means is a 1-bit binary counter and the second counter means is a 3-bit binary counter.

Claim 6

An apparatus claimed in claim 3 wherein the first counter means is a M-bit binary counter (where M is positive integer) and the second counter means is a N-bit binary counter (where N is positive integer not less than M).

Claim 7

An apparatus claimed in claim 3 wherein the selection means is a two-input multiplexor.

Claim 8

A data processing apparatus comprising: a program counter for designating the address of a microinstruction to be read; a decoder receiving the microinstruction stored at the address designated by the program counter for generating at least a first selection signal, a second selection signal, a first register address signal and a number-of-counter-selection signal; a first counter receiving a first timing signal and controlled by the first selection signal to count the first timing signal when the first selection signal is active so that the first counter generates a second register address signal incremented at each occurrence of the first timing signal; a multiplexor receiving the first and second register address signals and controlled by the first selection signal to select and output the second register address when the first selection signal is active; a register group including a plurality of registers and responsive to the first timing signal to latch the output of the multiplexor and to select a register designated by the output of the multiplexor; a second counter receiving the first timing signal and controlled by the second selection signal to count the first timing signal and controlled by the second selection signal to count the first timing signal when the second selection signal is active; and a comparator for comparing the count content of the second counter with the number-of-counter-selection signal and to reset the second counter when the content of the second counter becomes consistent with the number-of-counter-selection signal, with the result that the comparator itself generates one step-up signal to the program counter.

Claim 9

A data processing apparatus comprising: a program counter for designating the address of a microinstruction to be read; a decoder receiving the microinstruction stored at the address designated by the program counter for generating at least a first selection signal, a second selection signal, a first register address signal and a number-of-counter-selection signal; a first counter receiving a first timing signal and controlled by the first selection signal to count the first timing signal when the first selection signal is active so that the first counter generates a second register address signal incremented at each occurrence of the first timing signal; a multiplexor receiving the first and second register address signals and controlled by the first selection signal to select and output the second register address when the first selection signal is active; a register group including a plurality of registers and responsive to the first timing signal to latch the output of the multiplexor and to select a register designated by the output of the multiplexor; a second counter receiving the first timing signal and controlled by the second selection signal to count the first timing signal and controlled by the second selection signal to count the first timing signal when the second selection signal is active; and a comparator for comparing the count content of the second counter with the number-of-counter-selection signal and to reset the second counter when the content of the second counter becomes consistent with the number-of-counter-selection signal, with the result that the comparator itself generates one step-up signal to the program counter.

Claim 10

An apparatus claimed in claim 7 wherein the first counter means is a 1-bit binary counter and the second counter means is a 3-bit binary counter.

Claim 11

An apparatus claimed in claim 7 wherein the first counter means is a M-bit binary counter (where M is positive integer) and the second counter means is a N-bit binary counter (where N is positive integer not less than M).

Claim 12

A data processing apparatus comprising decoder means receiving a microinstruction to generate at least a first selection signal and a number-of-selection signal; first counter means receiving a timing signal and controlled by the first selection signal to generate a first register address signal updated at the timing signal; register means including a plurality of registers and receiving the first register address signal to select one of the registers designated by the register address signal; and means coupled to receive the number-of-selection signal and generating a microinstruction execution completion signal when the number of selections of the registers reaches the number indicated by the number-of-selection signal.

Claim 13

A data processing apparatus comprising decoder means receiving a microinstruction to generate at least a first selection signal and a number-of-selection signal; first counter means receiving a timing signal and controlled by the first selection signal to generate a first register address signal updated at the timing signal; register means including a plurality of registers and receiving the first register address signal to select one of the registers designated by the register address signal; and means coupled to receive the number-of-selection signal and generating a microinstruction execution completion signal when the number of selections of the registers reaches the number indicated by the number-of-selection signal.

Claim 14

An apparatus claimed in claim 10 wherein the microinstruction execution completion signal generating means includes second counter means operative to count the timing signal to generate the microinstruction execution completion signal when the number of selections of the registers reaches the number indicated by the number-of-selection signal.

Claim 15

An apparatus claimed in claim 11 wherein the second counter means includes a second counter operative to count up in response to the timing signal; and means comparing the content of the second counter with the number-of-selection signal to increment a program counter when the content of the second counter means becomes consistent with the number-of-selection signal.

Claim 16

An apparatus claimed in claim 12 wherein the decoder means further generates a second register address signal, and further including selection means receiving the first and second register address signals to output to the register means one of the first and second register address signals in response to the first selection signal.

Claim 17

An apparatus claimed in claim 13 wherein the decoder means is operative to further generate a second selection signal to the second counter means, and wherein the second counter means is conditioned for counting in response to the timing signal while the second selection signal is active, and is also reset by the comparator when the content of the second counter means becomes consistent with the number-of selection signal.