US4301514A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processor for processing at one time data including X bytes and Y bits
Assignee: Hitachi Ltd
•
Filing: 1979-09-25
•
Granted: 1981-11-17
•
Expires: 1999-09-25
Abstract
Abstract A high performance data processor being able to perform an address arithmetic at a high speed without enlarging the scale of the data processor for the increased number of bits of address data is disclosed.
Inventors
- 👤 Yoshiaki Eifuku
- 👤 Kazunobu Mimura
- 👤 Yasuyuki Okada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 03:47
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/57; G06F9/00; G06F9/06; G06F9/30; G06F9/34; G06F9/342; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/3808; G06F2207/3812; G06F2207/3816
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
116 words
A data processor comprising: a memory unit in which each word has the number of bits including X bytes+Y bits, and two words form one register; means for loading data to be loaded into the lower Y bits in the upper word also into the upper Y bits in the lower word when the result of the operand arithmetic is loaded into said register; an arithmetic unit capable of processing data in numbers of bits including X bytes+Y bits at a time; and means for reading out X bytes in the upper and lower words of said register separately when the data in said register is inputted into said arithmetic unit for executing the operand arithmetic.
Claim 2
Dependent Claim
116 words
A data processor comprising: a memory unit in which each word has the number of bits including X bytes+Y bits, and two words form one register; means for loading data to be loaded into the lower Y bits in the upper word also into the upper Y bits in the lower word when the result of the operand arithmetic is loaded into said register; an arithmetic unit capable of processing data in numbers of bits including X bytes+Y bits at a time; and means for reading out X bytes in the upper and lower words of said register separately when the data in said register is inputted into said arithmetic unit for executing the operand arithmetic.
Claim 3
Dependent Claim
27 words
A data processor according to claim 1, wherein said memory unit includes two banks with a common address and each bank has X bytes+Y bits assigned thereto.
Claim 4
Dependent Claim
53 words
A data processor according to claim 1, wherein said means for loading includes a data selector provided on a path for the upper Y bits of write-in data for said memory unit, and said data selector selects either the upper Y bit portion of the write-in data or the lower Y bit portion.
Claim 5
Dependent Claim
22 words
A data processor according to claim 1, wherein said arithmetic unit is used for both the operand arithmetic and the address arithmetic.
Claim 6
Dependent Claim
14 words
A data processor according to claim 1, wherein said register is a general register.
Claim 7
Dependent Claim
164 words
A data processor comprising: a memory unit in which each word has the number of bits including X bytes+Y bits and two words form one register; means for loading data to be loaded into the lower Y bits in the upper word also into the upper Y bits in the lower word when the result of the operand arithmetic is loaded into a register and for loading the result of the address arithmetic into the entire lower word of a register; an arithmetic unit capable of processing data the number of bits including X bytes+Y bits at a time; and means for reading out X bytes in the upper and lower words of the register separately when the data in the register is inputted into said arithmetic unit for executing the operand arithmetic, and for reading out the entire lower word of said register at a time when the data in said register is inputted into said arithmetic unit for executing the address arithmetic.
Claim 8
Dependent Claim
164 words
A data processor comprising: a memory unit in which each word has the number of bits including X bytes+Y bits and two words form one register; means for loading data to be loaded into the lower Y bits in the upper word also into the upper Y bits in the lower word when the result of the operand arithmetic is loaded into a register and for loading the result of the address arithmetic into the entire lower word of a register; an arithmetic unit capable of processing data the number of bits including X bytes+Y bits at a time; and means for reading out X bytes in the upper and lower words of the register separately when the data in the register is inputted into said arithmetic unit for executing the operand arithmetic, and for reading out the entire lower word of said register at a time when the data in said register is inputted into said arithmetic unit for executing the address arithmetic.
References Cited (Backward Citations)
US4021655A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-11-16 | 1985-05-18 | 1985-11-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-11-16 | 1989-05-18 | 1989-11-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-11-16 | 1993-05-18 | 1993-11-17 | $7700.00 | Window Closed / Lapsed |