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US4825347A
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Pulse width modulation control circuit
Assignee: Unisys Corp
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Filing: 1987-09-03
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Granted: 1989-04-25
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Expires: 2007-09-03
Abstract
Abstract A pulse width modulation control circuit utilizes a retriggerable monostable multivibrator as a high speed comparator which compares a reference waveform with a control signal level to effect variable termination of modulated output pulses. The control circuit finds particular applicability to pulse width modulated switched mode power supplies.
Inventors
- 👤 Nunzio Guerrera
- 👤 Lorenzo Cividino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 18:02
CPC Classifications
H; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/10; H02M3/145; H02M3/155; H02M3/156
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
203 words
Apparatus for providing output signal pulses having variable time durations comprising: clock means for generating a series of pulses with each pulse defining the initiation of an output signal pulse; means for generating a control signal having a signal level which is related to a desired time duration for a given output signal pulse; waveform means, coupled to the clock means, for generating a periodic signal having a period defined by the pulse repetition rate of the series of pulses generated by the clock means; summing means, having first and second inputs respectively coupled to the means for generating a control signal and the waveform means, operative to superimpose the periodic signal upon the control signal at a summing means output; and a monostable multivibrator circuit having a triggering input coupled to the clock means and an input conventionally coupled to a passive resistance/capacitive time period defining network instead coupled to the summing means output, the monostable multivibrator operative as connected to produce the output signal pulses, each pulse having a time duration extending from receipt at the triggering input of a clock pulse to attainment by the summing means output of a signal level determined by internal characteristics of the monostable multivibrator.
Claim 2
Dependent Claim
203 words
Apparatus for providing output signal pulses having variable time durations comprising: clock means for generating a series of pulses with each pulse defining the initiation of an output signal pulse; means for generating a control signal having a signal level which is related to a desired time duration for a given output signal pulse; waveform means, coupled to the clock means, for generating a periodic signal having a period defined by the pulse repetition rate of the series of pulses generated by the clock means; summing means, having first and second inputs respectively coupled to the means for generating a control signal and the waveform means, operative to superimpose the periodic signal upon the control signal at a summing means output; and a monostable multivibrator circuit having a triggering input coupled to the clock means and an input conventionally coupled to a passive resistance/capacitive time period defining network instead coupled to the summing means output, the monostable multivibrator operative as connected to produce the output signal pulses, each pulse having a time duration extending from receipt at the triggering input of a clock pulse to attainment by the summing means output of a signal level determined by internal characteristics of the monostable multivibrator.
Claim 3
Dependent Claim
16 words
Apparatus as set forth in claim 1 wherein the waveform means generates a saw-tooth periodic signal.
Claim 4
Dependent Claim
58 words
The apparatus of claim 2 wherein the means for generating a control signal comprises amplifier means having a first input coupled for receipt of a feedback signal, a second input coupled for receipt of a reference level, and an output carrying the control signal which is proportional to a difference between the feedback signal and the reference level.
Claim 5
Dependent Claim
29 words
The apparatus of claim 3 further comprising means for generating a peak current mode signal, the peak current mode signal coupled to a third input of the summing means.
Claim 6
Dependent Claim
47 words
The apparatus of claim 4 wherein the means for generating the peak current mode signal comprises a current sensing winding, and resistance means coupled to the current sensing winding for generating a peak current mode signal as a function of current flowing through the current sensing winding.
Claim 7
Dependent Claim
161 words
In a pulse width modulation circuit, the modulation effected by initiating a pulse with a signal from clock pulse train generating means, generating an error signal by comparing a monitored output to a first reference level, generating a control signal from the comparison results, superimposing a periodically increasing waveform upon the control signal to form a superimposed signal, comparing the superimposed signal with a second reference level, and terminating a pulse whenever the superimposed signal exceeds the second reference level, the improvement comprising: using a retriggerable, monostable multivibrator circuit having a variable activation time as means for comparing the superimposed signal with the second reference level by coupling the superimposed signal to an input of the multivibrator normally coupled to an external resistance-capacitance network for setting the activation time of the monostable circuit, the multivibrator operative as connected to internally generate the second reference level and to terminate a multivibrator output whenever the superimposed signal exceeds the internally generated reference level.
Claim 8
Dependent Claim
161 words
In a pulse width modulation circuit, the modulation effected by initiating a pulse with a signal from clock pulse train generating means, generating an error signal by comparing a monitored output to a first reference level, generating a control signal from the comparison results, superimposing a periodically increasing waveform upon the control signal to form a superimposed signal, comparing the superimposed signal with a second reference level, and terminating a pulse whenever the superimposed signal exceeds the second reference level, the improvement comprising: using a retriggerable, monostable multivibrator circuit having a variable activation time as means for comparing the superimposed signal with the second reference level by coupling the superimposed signal to an input of the multivibrator normally coupled to an external resistance-capacitance network for setting the activation time of the monostable circuit, the multivibrator operative as connected to internally generate the second reference level and to terminate a multivibrator output whenever the superimposed signal exceeds the internally generated reference level.
Claim 9
Dependent Claim
98 words
The improvement of claim 6 wherein the monostable multivibrator comprises a commercially available integrated circuit having an input conventionally designated in the semiconductor industry As "R EXT /C EXT ", coupled for receipt of the superimposed signal, an input conventionally designated "A" coupled to the clock pulse train generating means, inputs conventionally designated "V CC ", "B" and "CLR" each coupled to a source of positive bias voltage, inputs conventionally designated "C EXT " and "GND" each coupled to a source of ground potential, and an output conventionally designated "Q" serving as a source of modulated output pulses.
Claim 10
Dependent Claim
12 words
The improvement of claim 7 wherein the integrated circuit comprises type 74123.
Claim 11
Dependent Claim
78 words
The improvement of claim 6 wherein the monostable multivibrator comprises one of two multivibrators packaged in integrated circuit type SN74LS123, the integrated circuit package having pin 1 coupled for receipt of the clock pulse train, pin 15 coupled for receipt of the superimposed signal, pins 16, 2 and 3 each coupled to a source of positive bias voltage, pins 14 and 8 each coupled to ground potential, and pin 13 serving as the source of modulated output pulses.
Claim 12
Dependent Claim
78 words
The improvement of claim 6 wherein the monostable multivibrator comprises one of two multivibrators packaged in integrated circuit type SN74LS123, the integrated circuit package having pin 9 coupled for receipt of the clock pulse train, pin 7 coupled for receipt of the superimposed signal, pins 16, 10 and 11 each coupled to a source of positive bias voltage, pins 6 and 8 each coupled to ground potential, and pin 5 serving as the source of modulated output pulses.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-24 | 1992-10-24 | 1993-04-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-24 | 1996-10-24 | 1997-04-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-24 | 2000-10-24 | 2001-04-25 | $7700.00 | Window Closed / Lapsed |