US4825269A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Double heterojunction inversion base transistor
Assignee: Leland Stanford Junior University
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Filing: 1988-03-04
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Granted: 1989-04-25
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Expires: 2008-03-04
Abstract
Abstract A bipolar transistor in which the base region includes a heterostructure and a doped layer of semiconductor material with the heterostructure functioning as a two-dimensional hole gas. The doped layer is sufficiently thin to prevent occurrence of a charge-neutral region of holes. In operation the transistor can switch quickly since minority charge storage in the base region does not present a problem. The device lends itself to downscaling in size in a VLSI circuit.
Inventors
- 👤 James D. Plummer
- 👤 Robert C. Taft
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 04:49
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/80; H10D62/82; H10D62/822; H10D10/00; H10D10/80; H10D10/821; H10D10/841; H10D10/891
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
110 words
A transistor structure comprising: a first region of a first semiconductor material having a first conductivity type, said first region having a major surface, a second region of a second semiconductor material positioned on said major surface of said first region and forming a first heterojunction with said first region, a third region of said first semiconductor material positioned on said second region, said third region having an opposite conductivity type relative to said first conductivity type, said third region forming a second heterojunction with said second region, and a fourth region of said first semiconductor material having said first conductivity type, said fourth region positioned on said third region.
Claim 2
Dependent Claim
110 words
A transistor structure comprising: a first region of a first semiconductor material having a first conductivity type, said first region having a major surface, a second region of a second semiconductor material positioned on said major surface of said first region and forming a first heterojunction with said first region, a third region of said first semiconductor material positioned on said second region, said third region having an opposite conductivity type relative to said first conductivity type, said third region forming a second heterojunction with said second region, and a fourth region of said first semiconductor material having said first conductivity type, said fourth region positioned on said third region.
Claim 3
Dependent Claim
48 words
The transistor structure as defined by claim 1 and further including a first contact to said first region, a second contact to said second and third regions, and a third contact to said fourth region, said contacts functioning as collector, base, and emitter contacts for a bipolar transistor.
Claim 4
Dependent Claim
33 words
The transistor structure as defined by claim 2 wherein said first region comprises a substrate and at least one epitaxial layer formed on said substrate and said second region comprises a semiconductor alloy.
Claim 5
Dependent Claim
21 words
The transistor structure as defined by claim 3 wherein said first semiconductor material is silicon and said semiconductor alloy comprises germanium-silicon.
Claim 6
Dependent Claim
15 words
The transistor structure as defined by claim 3 wherein said structure includes a mesa structure.
Claim 7
Dependent Claim
23 words
The transistor structure as defined by claim 5 wherein said substrate functions as a mechanical support for a plurality of said transistor structures.
Claim 8
Dependent Claim
33 words
The transistor structure as defined by claim 1 wherein said first region comprises a substrate and at least one epitaxial layer formed on said substrate and said second region comprises a semiconductor alloy.
Claim 9
Dependent Claim
15 words
The transistor structure as defined by claim 7 wherein said structure includes a mesa structure.
Claim 10
Dependent Claim
23 words
The transistor structure as defined by claim 8 wherein said substrate functions as a mechanical support for a plurality of said transistor structures.
Claim 11
Dependent Claim
53 words
The transistor structure as defined by claim 1 wherein said first region comprises an n-type silicon substrate and first and second n-type epitaxial layers on said substrate, said second region comprises a germanium-silicon alloy, said third region comprises a layer of p-type silicon, and said fourth region comprises two layers of n-type silicon.
Claim 12
Dependent Claim
170 words
The transistor structure as defined by claim 10 wherein one of said n-type epitaxial layers has a thickness on the order of 1.2 microns and a dopant concentration on the order of 2×10 19 atoms per cubic centimeter and the other epitaxial layer has a thickness on the order of 2600 Angstroms and a dopant concentration on the order of 1×10 17 atoms per cubic centimeter, said second region is a layer having a thickness on the order of 100 Å, said layer of p-type material has a thickness on the order of 50 Å and a dopant concentration on the order of 1×10 19 atoms per cubic centimeter, one of said two layers of said fourth region having a thickness on the order of 350 Å and a dopant concentration on the order of 1×10 18 atoms per cubic centimeter and the other of said layers having a thickness on the order of 800 Å and a dopant concentration on the order of 3×10 19 atoms per cubic centimeter.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-24 | 1992-10-24 | 1993-04-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-24 | 1996-10-24 | 1997-04-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-24 | 2000-10-24 | 2001-04-25 | $7700.00 | Window Closed / Lapsed |