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US4823260A
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Mixed-precision floating point operations from a single instruction opcode
Assignee: Intel Corp
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Filing: 1987-11-12
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Granted: 1989-04-18
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Expires: 2007-11-12
Abstract
Abstract Apparatus for performing mixed precision calculations in the floating point unit of a microprocessor from a single instruction opcode. 80-bit floating-point registers (44) may be specified as the source or destination address of a floating-point instruction. When the address range of the destination indicates (26) that a floating point register is addressed, the result of that operation is not rounded to the precision specified by the instruction, but is rounded (58) to extended 80-bit precision and loaded into the floating point register (FP-44). When the address range of the source indicates (26) that an FP register is addressed, the data is loaded from the FP register in extended precision, regardless of the precision specified by the instruction. In this way, real and long-real operations can be made to use extended precision numbers without explicitly specifying that in the opcode.
Inventors
- 👤 Michael T. Imel
- 👤 Konrad Lai
- 👤 Glenford J. Myers
- 👤 Randy Steck
- 👤 James Valerio
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 15:44
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/483; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/3001; G06F9/30014; G06F9/30098; G06F9/3012; G06F9/3013; G06F9/30145; G06F9/3016; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/3808; G06F2207/3812; G06F2207/3816; G06F7/499; G06F7/49942; G06F7/49947; G06F7/49957
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
146 words
In a data processor including an instruction decoder (12) and a floating point unit (22) connected together by a microinstruction bus (29) which carries a current microinstruction generated by said decoder in the course of the decoding of a macroinstruction by said decoder, said macroinstruction including a source address field, a destination address field, and an opcode field, said opcode field including first means (LL0, LL1) specifying the precision of arithmetic operations specified by said macroinstruction, the improvement characterized by: said microinstruction generated by said instruction decoder (12) including second means (opcode 1) for indicating that the address range of said source or destination address in said macroinstruction includes the address of a floating point register (44) in said floating point unit 22; and, third means (73, 75) responsive to said second means (opcode 1) for modifying said first means (LL0, LL1) to specify extended precision.
Claim 2
Dependent Claim
146 words
In a data processor including an instruction decoder (12) and a floating point unit (22) connected together by a microinstruction bus (29) which carries a current microinstruction generated by said decoder in the course of the decoding of a macroinstruction by said decoder, said macroinstruction including a source address field, a destination address field, and an opcode field, said opcode field including first means (LL0, LL1) specifying the precision of arithmetic operations specified by said macroinstruction, the improvement characterized by: said microinstruction generated by said instruction decoder (12) including second means (opcode 1) for indicating that the address range of said source or destination address in said macroinstruction includes the address of a floating point register (44) in said floating point unit 22; and, third means (73, 75) responsive to said second means (opcode 1) for modifying said first means (LL0, LL1) to specify extended precision.
Claim 3
Dependent Claim
62 words
The data processor of claim 1 wherein a pair of round precision bits (RND PREC 0, RND PREC 1) specify rounding modes of operation, further characterized by: fourth means (85) responsive to said one bit for forcing said round precision bits to a value (84, 86) specifying an extended precision mode of operation upon the condition that said one bit is asserted.
Claim 4
Dependent Claim
106 words
The data processor of claim 1 further characterized by: said first means in said opcode field being a pair of bits (LL1, LL2) specifying four precisions of arithmetic operations; said instruction decoder (12) generating a microinstruction, one bit (opcode 1) of which specifies when asserted, that the address range of said source or destination address in said macroinstruction specify a floating point register (44) in said floating point unit (22); and, said third means (73, 75) is responsive to said one bit and forces said LL bits to a value (80, 82) specifying extended precision upon the condition that said one bit (opcode 1) is asserted.
Claim 5
Dependent Claim
60 words
The data processor of claim 3 wherein a pair of round precision bits (RND PREC 0, RND PREC 1) specify rounding modes of operation, further characterized by: fourth means (85) responsive to said one bit (opcode 1) for forcing said round precision bits to a value (84, 86) specifying extended precision upon the condition that said one bit is asserted.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-17 | 1992-10-17 | 1993-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-17 | 1996-10-17 | 1997-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-17 | 2000-10-17 | 2001-04-18 | $7700.00 | Window Closed / Lapsed |