MOS transconductance amplifier for active filters

Claim 2

A differential input transconductor including a pair of field-effect transistors each having a substrate terminal, a source terminal, a gate terminal and a drain terminal, wherein the source terminals of the pair are connected together to a first fixed voltage; the substrate terminals of the pair are connected to a second fixed voltage; means is provided to set equal quiescent voltages on the gate terminals and to superimpose equal but opposite signal voltages on the two gate terminals; and means is provided to maintain the voltages on the drain terminals of the two transistors at an equal voltage chosen to keep the transistors in the triode region of operation for the expected variation of the gate-source voltage, the drain terminals of the pair of transistors being connected to an output circuit to maintain the voltage on the drain terminals at the chosen voltage and to transmit a differential mode output current component of the transconductor via output terminals to a load circuit at a higher impedance level, the output circuit comprising a first pair of transistors each defining a common-gate MOS stage and the output circuit including a further pair of transistors each of which is connected to a respective one of the first pair of transistors of the MOS stage, said first pair and said further pair being of opposite polarity type and being connected together in a feedback loop such that the input impedance seen at the drain terminals of the pair of field effect transistors is reduced below that of the common-gate MOS stage by a factor equal to the loop gain of the feedback loop.

Claim 3

A differential input transconductor including a pair of field-effect transistors each having a substrate terminal, a source terminal, a gate terminal and a drain terminal, wherein the source terminals of the pair are connected together to a first fixed voltage; the substrate terminals of the pair are connected to a second fixed voltage; means is provided to set equal quiescent voltages on the gate terminals and to superimpose equal but opposite signal voltages on the two gate terminals; and means is provided to maintain the voltages on the drain terminals of the two transistors at an equal voltage chosen to keep the transistors in the triode region of operation for the expected variation of the gate-source voltage, a pair of capacitors being connected between respective drain terminals of each transistor and the gate terminal of the opposite transistor, to minimize the phase delay between the input voltage and the output current of the transconductor.

Claim 4

A differential input transconductor including a pair of field-effect transistors each having a substrate terminal, a source terminal, a gate terminal and a drain terminal, wherein the source terminals of the pair are connected together to a first fixed voltage; the substrate terminals of the pair are connected to a second fixed voltage; means is provided to set equal quiescent voltages on the gate terminals and to superimpose equal but opposite signal voltages on the two gate terminals; and means is provided to maintain the voltages on the drain terminals of the two transistors at an equal voltage chosen to keep the transistors in the triode region of operation for the expected variation of the gate-source voltage, a pair of capacitors being connected between respective drain terminals of each transistor and the gate terminal of the opposite transistor, to minimize the phase delay between the input voltage and the output current of the transconductor.

Claim 5

A differential input transconductor including a pair of field-effect transistors each having a substrate terminal, a source terminal, a gate terminal and a drain terminal, wherein the source terminals of the pair are connected together to a first fixed voltage; the substrate terminals of the pair are connected to a second fixed voltage; means is provided to set equal quiescent voltages on the gate terminals and to superimpose equal but opposite signal voltages on the two gate terminals; and means is provided to maintain the voltages on the drain terminals of the two transistors at an equal voltage chosen to keep the transistors in the triode region of operation for the expected variation of the gate-source voltage, the drain terminals of the pair of transistors being connected to an output circuit to maintain the voltage on the drain terminals at the chosen voltage and to transmit a differential mode output current component of the transconductor via output terminals to a load circuit at a higher impedance level, the voltages at the output terminals being applied to the inputs of a summing amplifier stage to give an output signal representing the common-mode component of the output terminal voltages, and this output signal controlling a pair of current sources injecting equal currents into respective nodes of two symmetric halves of the transconductor, the polarity of these currents being such as to stabilize the common-mode component of the output voltages.

Claim 6

A differential input transconductor including a pair of field-effect transistors each having a substrate terminal, a source terminal, a gate terminal and a drain terminal, wherein the source terminals of the pair are connected together to a first fixed voltage; the substrate terminals of the pair are connected to a second fixed voltage; means is provided to set equal quiescent voltages on the gate terminals and to superimpose equal but opposite signal voltages on the two gate terminals; and means is provided to maintain the voltages on the drain terminals of the two transistors at an equal voltage chosen to keep the transistors in the triode region of operation for the expected variation of the gate-source voltage, the drain terminals of the pair of transistors being connected to an output circuit to maintain the voltage on the drain terminals at the chosen voltage and to transmit a differential mode output current component of the transconductor via output terminals to a load circuit at a higher impedance level, the voltages at the output terminals being applied to the inputs of a summing amplifier stage to give an output signal representing the common-mode component of the output terminal voltages, and this output signal controlling a pair of current sources injecting equal currents into respective nodes of two symmetric halves of the transconductor, the polarity of these currents being such as to stabilize the common-mode component of the output voltages.

Claim 7

A differential input transconductor including a pair of field-effect transistors each having a substrate terminal, a source terminal, a gate terminal and a drain terminal, wherein the source terminals of the pair are connected together to a first fixed voltage; the substrate terminals of the pair are connected to a second fixed voltage; means is provided to set equal quiescent voltages on the gate terminals and to superimpose equal but opposite signal voltages on the two gate terminals; the drain terminal of each one of the pair of field-effect transistors is connected to a respective emitter of a first pair of bipolar transistors; means is provided to maintain the base terminals of the bipolar transistor of the first pair of bipolar transistors at a constant voltage chosen so that the field-effect transistors remain biased in the triode region of operation over the expected variation in gate-source voltage; the collector terminal of each of the bipolar transistors of the first pair of bipolar transistors is connected to a respective one of a first pair of current sources and to the base terminal of the respective one of a second pair of bipolar transistors, the second pair of bipolar transistors being of opposite polarity type to the first pair of bipolar transistors; the collector of each said respective second pair of bipolar transistors being connected to the emitter of the said respective bipolar transistor of the first pair of bipolar transistors; the emitter of each of said second pair of bipolar transistors being connected to the emitter of a respective one of a third pair of transistors having respective collector terminals and also to the respective one of a second pair of current sources; output currents being taken from each of the collectors of the third pair of transistors, via a respective output terminal.

Claim 8

A differential input transconductor including a pair of field-effect transistors each having a substrate terminal, a source terminal, a gate terminal and a drain terminal, wherein the source terminals of the pair are connected together to a first fixed voltage; the substrate terminals of the pair are connected to a second fixed voltage; means is provided to set equal quiescent voltages on the gate terminals and to superimpose equal but opposite signal voltages on the two gate terminals; the drain terminal of each one of the pair of field-effect transistors is connected to a respective emitter of a first pair of bipolar transistors; means is provided to maintain the base terminals of the bipolar transistor of the first pair of bipolar transistors at a constant voltage chosen so that the field-effect transistors remain biased in the triode region of operation over the expected variation in gate-source voltage; the collector terminal of each of the bipolar transistors of the first pair of bipolar transistors is connected to a respective one of a first pair of current sources and to the base terminal of the respective one of a second pair of bipolar transistors, the second pair of bipolar transistors being of opposite polarity type to the first pair of bipolar transistors; the collector of each said respective second pair of bipolar transistors being connected to the emitter of the said respective bipolar transistor of the first pair of bipolar transistors; the emitter of each of said second pair of bipolar transistors being connected to the emitter of a respective one of a third pair of transistors having respective collector terminals and also to the respective one of a second pair of current sources; output currents being taken from each of the collectors of the third pair of transistors, via a respective output terminal.