Multilevel logic circuit with floating node voltage clamp

Claim 2

In a buffer circuit comprising a switch and at least one transistor having a control terminal for receiving an input signal, a first load terminal resistively coupled to a voltage source, and a second load terminal, the switch alternatively coupling a current source to and uncoupling the current source from the second load terminal in response to a control signal, the improvement comprising clamping means responsive to said control signal for maintaining a substantially constant voltage at said second load terminal while the switch decouples the current source from the second load terminal, the constant voltage being substantially equal to a steady-state voltage produced at said second load terminal when the switch couples the current source to the second load terminal.

Claim 3

A circuit for selectively buffering an input signal in response to a control signal, the circuit comprising: a current source; buffer means for producing an output signal in response to the input signal when the current source is coupled to a first node of the buffer means; and means responsive to the control signal for selectively coupling the first node to the current source when the control signal is of a first level, for uncoupling the first node from the current source when the control signal is of a second level, and for maintaining a constant voltage on the first node when the control signal is of the second level.

Claim 4

A circuit for selectively buffering an input signal in response to a control signal, the circuit comprising: a current source; buffer means for producing an output signal in response to the input signal when the current source is coupled to a first node of the buffer means; and means responsive to the control signal for selectively coupling the first node to the current source when the control signal is of a first level, for uncoupling the first node from the current source when the control signal is of a second level, and for maintaining a constant voltage on the first node when the control signal is of the second level.

Claim 5

The circuit in accordance with claim 1 wherein the constant voltage is substantially equal to a steady-state voltage produced at the first node when the current source is connected to the first node.

Claim 6

The circuit in accordance with claim 1 wherein the means responsive to the control signal comprises: switch means for selectively coupling the first node to the current source when the control signal is of the first level; means for producing at a second node a reference voltage of a third level when the control signal is of the first level, and for producing the reference voltage of a fourth level when the control signal is of the second level; and a diode connected between the first and second nodes, the diode being reverse biased when the reference voltage is of the second level and forward biased when the reference voltage is of the fourth level.

Claim 7

The circuit in accordance with claim 4 wherein the fourth level of the reference voltage differs from a steady-state voltage produced at the first node when the current source is connected to the first node, the reference voltage and steady-state voltages differing by an amount approximately equal to a forward bias voltage of the diode.

Claim 8

The circuit in accordance with claim 2 wherein said buffer means comprises: a load resistor; a source of supply voltage; and at least one transistor having a control terminal for receiving the input signal and having first and second load terminals, the load resistor coupling the first load terminal of the first transistor to the source of supply voltage, the second load terminal of the first transistor being coupled to the first node.

Claim 9

The circuit in accordance with claim 6 wherein said means responsive to the control signal comprises: switch means for selectively coupling the first node to the current source when the control signal is of the first level; means for producing at a second node a reference voltage of a third level when the control signal is of the first level and for producing the reference voltage of a fourth level when the control signal is of the second level; and a diode connected between the first and second nodes, the diode being reverse biased when the reference voltage is of the second level and forward biased when the reference voltage is of the fourth level.

Claim 10

The circuit in accordance with claim 7 wherein the switch means comprises a second transistor having a control terminal for receiving the control signal, having a first load terminal coupled to the first node and having a second load terminal coupled to the current source.

Claim 11

A multilevel logic circuit for selectively buffering an input signal in response to a control signal, the logic circuit comprising: first current source means for producing a substantially constant current; a first load resistor; a second load resistor; a source of supply voltage; a first transistor having a control terminal and first and second load terminals; a second transistor having a control terminal and first and second load terminals, the first and second load resistors respectively coupling the first load terminals of the first and second transistors to the source of supply voltage, the second load terminals of the first and second transistors being coupled one to another, the input signal being applied across the control terminals of the first and second transistors; a circuit node; second current source means connected to the circuit node for selectively providing a current through the circuit node in response to the control signal; a third load resistor; a first diode, the first diode and the third load resistor being connected in series between the source of supply voltage and the circuit node; a second diode coupling the second load terminals of the first and second transistors to the circuit node; and means for selectively connecting the first current source means to the second load terminals of the first and second transistors in response to the control signal.

Claim 12

A multilevel logic circuit for selectively buffering an input signal in response to a control signal, the logic circuit comprising: first current source means for producing a substantially constant current; a first load resistor; a second load resistor; a source of supply voltage; a first transistor having a control terminal and first and second load terminals; a second transistor having a control terminal and first and second load terminals, the first and second load resistors respectively coupling the first load terminals of the first and second transistors to the source of supply voltage, the second load terminals of the first and second transistors being coupled one to another, the input signal being applied across the control terminals of the first and second transistors; a circuit node; second current source means connected to the circuit node for selectively providing a current through the circuit node in response to the control signal; a third load resistor; a first diode, the first diode and the third load resistor being connected in series between the source of supply voltage and the circuit node; a second diode coupling the second load terminals of the first and second transistors to the circuit node; and means for selectively connecting the first current source means to the second load terminals of the first and second transistors in response to the control signal.

Claim 13

A multilevel logic circuit comprising: a circuit node; a current source; a source of supply voltage; a load resistor; a first transistor, having a control terminal for receiving an input signal and having first and second load terminals, the load resistor coupling the first load terminal of the first transistor to the source of supply voltage, the second load terminal of the first transistor being coupled to the circuit node; a second transistor, having a control terminal for receiving a control signal and having first and second load terminals, the first load terminal of the second transistor being coupled to the circuit node, the second load terminal of the second transistor being coupled to the current source, the second transistor providing a path of low impedance between its first and second load terminals when the control signal is of a first level and providing a high impedance path between its first and second load terminals when the control signal is of a second level; and clamping means responsive to the control signal for selectively clamping the circuit node to a constant voltage when the control signal is of the second level.

Claim 14

A multilevel logic circuit comprising: a circuit node; a current source; a source of supply voltage; a load resistor; a first transistor, having a control terminal for receiving an input signal and having first and second load terminals, the load resistor coupling the first load terminal of the first transistor to the source of supply voltage, the second load terminal of the first transistor being coupled to the circuit node; a second transistor, having a control terminal for receiving a control signal and having first and second load terminals, the first load terminal of the second transistor being coupled to the circuit node, the second load terminal of the second transistor being coupled to the current source, the second transistor providing a path of low impedance between its first and second load terminals when the control signal is of a first level and providing a high impedance path between its first and second load terminals when the control signal is of a second level; and clamping means responsive to the control signal for selectively clamping the circuit node to a constant voltage when the control signal is of the second level.

Claim 15

The circuit of claim 10 wherein the clamping means comprises; a source of the reference voltage, the reference voltage being of magnitude determined by the control signal; and diode means connecting the source of reference voltage to the circuit node, the reference voltage being of magnitude such that the diode is forward biased when the control signal is of the second level and reverse biased when the control signal is of the first level.

Claim 16

A latch comprising: a current source for providing a control current; a buffer having a first circuit node for receiving said control current and producing as output a first differential signal in response to an input differential signal when said control current is applied to said first circuit node; a regenerative circuit having a second circuit node for receiving said control current and producing as output a second differential signal in response to said first differential signal when said control current is applied to said second circuit node; switch means for alternatively applying said control current to said first and second circuit nodes in accordance with a control signal; and clamping means responsive to said control signal for maintaining said first circuit node at a first constant voltage when the control current is applied to said second circuit node and for maintaining said second circuit node at a second constant voltage when said control current is applied to said first circuit node.

Claim 17

A latch comprising: a current source for providing a control current; a buffer having a first circuit node for receiving said control current and producing as output a first differential signal in response to an input differential signal when said control current is applied to said first circuit node; a regenerative circuit having a second circuit node for receiving said control current and producing as output a second differential signal in response to said first differential signal when said control current is applied to said second circuit node; switch means for alternatively applying said control current to said first and second circuit nodes in accordance with a control signal; and clamping means responsive to said control signal for maintaining said first circuit node at a first constant voltage when the control current is applied to said second circuit node and for maintaining said second circuit node at a second constant voltage when said control current is applied to said first circuit node.

Claim 18

The latch in accordance with claim 12 wherein said first constant voltage is substantially equal to a first steady-state voltage produced at said first circuit node when said control current is applied to said first circuit node, and wherein said second constant voltage is substantially equal to a second steady-state voltage produced at said second circuit node when said control current is applied to said second circuit node.