Patent US4822754A successfully refreshed from Google Patents.
US4822754A
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US
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Fabrication of FETs with source and drain contacts aligned with the gate electrode
Assignee: Nokia Bell Labs
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Filing: 1984-06-12
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Granted: 1989-04-18
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Expires: 2004-06-12
Abstract
Abstract A method of fabricating FETs to reduce parasitics. Contact is made to the source and drain regions through a polycrystalline silicon runner which is aligned with the edge of the gate electrode. This is accomplished by providing a multi-level electrode structure including a gate electrode and depositing the polycrystalline silicon layer over the device. The polycrystalline silicon is rendered selectively removable in the portion overlying the gate electrode. When this portion is removed, the remaining polycrystalline is aligned with the gate.
Inventors
- 👤 William T. Lynch
- 👤 Frederick Vratny
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 03:43
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D62/00; H10D62/80; H10D62/83; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10D64/60; H10D64/62
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
96 words
A method of fabricating a field effect transistor including a source and drain region formed in the surface of a semiconductor substrate with a channel region therebetween, the method comprising the steps of: forming over the channel region a multi-level electrode structure including a gate electrode metal; forming an insulator along the edges of at least the gate electrode metal; depositing a layer of polycrystalline silicon over essentially the entire transistor area; rendering the portion of the polycrystalline silicon layer over the gate electrode selectively removable; and selectively removing the said portion of the polycrystalline layer.
Claim 2
Independent Claim
96 words
A method of fabricating a field effect transistor including a source and drain region formed in the surface of a semiconductor substrate with a channel region therebetween, the method comprising the steps of: forming over the channel region a multi-level electrode structure including a gate electrode metal; forming an insulator along the edges of at least the gate electrode metal; depositing a layer of polycrystalline silicon over essentially the entire transistor area; rendering the portion of the polycrystalline silicon layer over the gate electrode selectively removable; and selectively removing the said portion of the polycrystalline layer.
Claim 3
Dependent Claim
46 words
The method according to claim 1 wherein the multi-level electrode structure includes a top layer which is a material including a dopant impurity and the portion of the polysilicon is rendered selectively removable by diffusion of the dopant into the said portion of the polycrystalline layer.
Claim 4
Dependent Claim
17 words
The method according to claim 2 wherein the top layer comprises a polycrystalline layer doped with phosphorous.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-17 | 1992-10-17 | 1993-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-17 | 1996-10-17 | 1997-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-17 | 2000-10-17 | 2001-04-18 | $7700.00 | Window Closed / Lapsed |