Patent US4821237A successfully refreshed from Google Patents.
US4821237A
Expired / Lapsed
US
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Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1986-12-18
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Granted: 1989-04-11
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Expires: 2006-12-18
Abstract
Abstract This invention provides a semiconductor memory device for reading and writing data comprising a pair of row lines, each having a corresponding electrical potential, the difference between the two potentials increasing during reading of data at least one static memory cell connected between the pair of row lines for storing data written into the memory cell and voltage control means for limiting the increase in the potential difference between the row lines during reading of the data from the memory cell to a predetermined amount for getting fast access time of the reading operation.
Inventors
- 👤 Hiroshi Iwahashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:00
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C7/00; G11C7/12; G11C11/41; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
111 words
A semiconductor memory device for reading and writing data comprising: a pair of row lines, each having a corresponding electrical potential, the difference between the two potentials increasing during reading of data; at least one static memory cell connected between the pair of row lines for storing data written into the memory cell; switching means for connecting the static memory cell to the row lines in accordance with a selecting signal; and voltage control means for limiting the increase in the potential difference between the row lines to perform the reading of the data from the memory cell at a predetermined restricted potential allowing fast access time during the reading operation.
Claim 2
Dependent Claim
111 words
A semiconductor memory device for reading and writing data comprising: a pair of row lines, each having a corresponding electrical potential, the difference between the two potentials increasing during reading of data; at least one static memory cell connected between the pair of row lines for storing data written into the memory cell; switching means for connecting the static memory cell to the row lines in accordance with a selecting signal; and voltage control means for limiting the increase in the potential difference between the row lines to perform the reading of the data from the memory cell at a predetermined restricted potential allowing fast access time during the reading operation.
Claim 3
Dependent Claim
51 words
The semiconductor memory device according to claim 1 wherein the voltage control means includes two MOS transistors coupled in parallel between the pair of row lines, the drains and gates of the two transistors being connected together and the drain of one transistor being connected to the source of the other.
Claim 4
Dependent Claim
56 words
The semiconductor memory device according to claim 2 wherein the voltage control means also includes a MOS switching transistor coupled in series to the two MOS transistors, the switching transistor being in the ON state when data is read from the memory cell, and in the OFF state when data is written into the memory cell.
Claim 5
Dependent Claim
23 words
The semiconductor memory device according to claim 2 wherein each of the two MOS transistors has a threshold voltage of about 0 (V).
Claim 6
Dependent Claim
56 words
The semiconductor memory device according to claim 4 wherein the voltage control means also includes a MOS switching transistor coupled in series to the two MOS transistors, the switching transistor being in the ON state when data is read from the memory cell, and in the OFF state when data is written into the memory cell.
Claim 7
Dependent Claim
41 words
The semiconductor memory device according to claim 1 wherein the voltage control means includes an enhancement type MOS transistor coupled between the pair of row lines, and wherein a prescribed voltage is applied to the gate of the the enhancement transistor.
Claim 8
Dependent Claim
57 words
The semiconductor memory device according to claim 6 wherein the voltage control means also includes a MOS switching transistor coupled in series to the enhancement type MOS transistor, the switching transistor being in the ON state when data is read from the memory cell, and in the OFF state when data is written into the memory cell.
Claim 9
Dependent Claim
35 words
The semiconductor memory device according to claim 1 wherein the voltage control means includes a depletion type MOS transistor coupled between the pair of row lines having a prescribed voltage applied to the gate thereof.
Claim 10
Dependent Claim
57 words
The semiconductor memory device according to claim 8 wherein the voltage control means also includes a MOS switching transistor coupled in series to the depletion type MOS transistor, the switching transistor being in the ON state when data is read from the memory cell, and in the OFF state when data is written into the memory cell.
Claim 11
Dependent Claim
29 words
The semiconductor memory device according to claim 1 wherein the voltage control means limits the increase in the potential difference at least prior to the reading of the data.
Claim 12
Dependent Claim
26 words
The semiconductor memory device according to claim 1 wherein the voltage control means limits the increase in the potential difference after the reading of the data.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-10 | 1992-10-10 | 1993-04-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-10 | 1996-10-10 | 1997-04-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-10 | 2000-10-10 | 2001-04-11 | $7700.00 | Window Closed / Lapsed |