Arithmetic and logic unit with prior state dependent logic operations

Claim 1

An arithmetic and logic unit capable of selectively executing one of predetermined logical operations responsive to an operating condition signal generated by an earlier logical operation of said arithmetic logic unit, thereby minimizing the need for branch on condition operations, said arithmetic and logic unit comprising: first storage means for storing a portion of said operating condition signal generated during an earlier operation of said arithmetic and logic unit, said first storage means capable of storing three states representing "positive", "negative" and "zero" conditions, second storage means for storing a remaining portion of said operating condition signal, said second storage means capable of storing three states representing respectively said "positive", "negative" and "zero" conditions, a control circuit for selectively outputting "addition", "subtraction" and "no operation" control signals in response to said states stored in said first and second storage means, and an arithmetic and logic circuit for performing arithmetic operations responsive to said control signals output by said control circuit and for generating a new operating condition signal.