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US4821179A
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Communication system configuration detection apparatus and method
Assignee: Avaya Technology LLC
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Filing: 1985-08-08
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Granted: 1989-04-11
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Expires: 2005-08-08
Abstract
Abstract A data processing system includes a processor unit (CPU) connected over a CPU bus to a plurality of memory components, but is not connected to any input-output (I/O) component of the system. The system I/O component(s) connect to the memories over an I/O bus. A method and apparatus is disclosed for selecting one of the memories to be used for communications between the processor unit and the I/O components. Also, a method for determining which I/O components are in the system.
Inventors
- 👤 Craig W. Jensen
- 👤 Frederick R. Keller
- 👤 Joel I. Morrow
- 👤 Eric A. Roth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:48
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/44; G06F9/4401; G06F9/4411; G06F15/00; G06F15/16; G06F15/177
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
139 words
In a data processing system including a processor connected over a CPU bus to a plurality of read/write memories, said memories connected over an I/O bus to an I/O interface and wherein said CPU bus connects to said I/O bus using said memories, a method of selecting one of said memories for enabling communication between said processor and said I/O interface comprising the steps of: in said processor selecting in response to a control signal one of said memories as a selected memory using a particular selection rule, sending an initialize signal to said I/O interface, checking said selected memory for a response from said I/O interface and in said I/O interface determining using said particular selection rule and in response to said initialize signal, which one of said memories is to store said response from said I/O interface.
Claim 2
Dependent Claim
139 words
In a data processing system including a processor connected over a CPU bus to a plurality of read/write memories, said memories connected over an I/O bus to an I/O interface and wherein said CPU bus connects to said I/O bus using said memories, a method of selecting one of said memories for enabling communication between said processor and said I/O interface comprising the steps of: in said processor selecting in response to a control signal one of said memories as a selected memory using a particular selection rule, sending an initialize signal to said I/O interface, checking said selected memory for a response from said I/O interface and in said I/O interface determining using said particular selection rule and in response to said initialize signal, which one of said memories is to store said response from said I/O interface.
Claim 3
Dependent Claim
21 words
The method of claim 1 wherein said checking step is performed at a defined device communication area of said selected memory.
Claim 4
Dependent Claim
25 words
The method of claim 1 wherein said checking step waits for a given period of time before checking the defined area of said selected memory.
Claim 5
Dependent Claim
18 words
The method of claim 1 wherein said selected memory is selected in response to a system power-up signal.
Claim 6
Dependent Claim
89 words
The method of claim 1 wherein said system includes two or more I/O interfaces and no response is obtained in said selected memory from said I/O interfaces during said checking step, said system including the steps of: disconnecting each of said I/O interfaces from said I/O bus, initializing a defined device communication area of each of said memories, reinitializing each of said I/O interfaces, and wherein said checking step further checks each of said memories for responses to determine if responses are contained in only one of said memories.
Claim 7
Dependent Claim
32 words
The method of claim 5 further including the step of: outputting an error message when said checking step determines that more than one of said memories contain responses from said I/O interfaces.
Claim 8
Dependent Claim
35 words
The method of claim 5 further including the step of: selecting one of said memories for communications between said processor and said I/O interfaces when said selected memory received all responses from said I/O interfaces.
Claim 9
Dependent Claim
141 words
A data processing system including a processor connected over a CPU bus to a plurality of read/write memories, said memories connected over an I/O bus to an I/O interface, wherein said CPU bus is not connected to said I/O bus, and wherein said processor communicates with said I/O interface via a selected one of said memories, said system further comprising in said processor means for selecting in response to a control signal one of said memories as a selected memory using a particular selection rule, means for sending an initialize signal to said I/O interface, means for checking said selected memory for a response from said I/O interface and in said I/O interface means using said particular selection rule and responsive to said initialize signal for determining which one of said memories is to store said response from said I/O interface.
Claim 10
Dependent Claim
141 words
A data processing system including a processor connected over a CPU bus to a plurality of read/write memories, said memories connected over an I/O bus to an I/O interface, wherein said CPU bus is not connected to said I/O bus, and wherein said processor communicates with said I/O interface via a selected one of said memories, said system further comprising in said processor means for selecting in response to a control signal one of said memories as a selected memory using a particular selection rule, means for sending an initialize signal to said I/O interface, means for checking said selected memory for a response from said I/O interface and in said I/O interface means using said particular selection rule and responsive to said initialize signal for determining which one of said memories is to store said response from said I/O interface.
Claim 11
Dependent Claim
79 words
The data processing system of claim 8 including two or more of said I/O interfaces, said system further comprising means for disconnecting each of said I/O interfaces from said I/O bus, means for initializing a device communication area of each of said memories, means for reinitializing each of said I/O interfaces, and means for selecting one of said memories for communications between said processor and said I/O interface when said selected memory received all responses from said I/O interfaces.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-10 | 1992-10-10 | 1993-04-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-10 | 1996-10-10 | 1997-04-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-10 | 2000-10-10 | 2001-04-11 | $7700.00 | Window Closed / Lapsed |