US4820997A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Differential amplifier circuit
Assignee: Hitachi Ltd
•
Filing: 1987-03-02
•
Granted: 1989-04-11
•
Expires: 2007-03-02
Abstract
Abstract A differential amplifier circuit including not only first and second transistors whose emitters are coupled together through a resistor to form a differential transistor pair, but also first and second distortion-correcting transistors, is disclosed. In this circuit, the base terminal of the first transistor is connected to the emitter terminal of the first distortion-correcting transistor, the base terminal of the second transistor is connected to the emitter terminal of the second distortion-correcting transistor, the emitter terminals of the first and second distortion-correcting transistors are connected to a current source of the current control type, and a ratio of the current flowing through the first distortion-correcting transistor to the current flowing through the second distortion-correcting transistor is made equal to a ratio of the emitter current of the second transistor to the emitter current of the first transistor, to cancel the non-linear distortion due to the base-to-emitter voltages of the first and second transistors by the non-linear distortion due to the base-to-emitter voltages of the first and second distortion-correcting transistors, thereby eliminating non-linear distortion from the output of the differential amplifier circuit.
Inventors
- 👤 Yuji Sano
- 👤 Michitaka Osawa
- 👤 Masahide Kawai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 07:25
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F1/00; H03F1/32; H03F1/3211
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
216 words
A differential amplifier arrangement comprising: first and second input terminals between which a signal source is connected; a differential amplifier circuit having first and second transistors, each having collector, base and emitter electrodes, said emitters of said first and second transistors being connected together, wherein an output voltage is derived from at least one of said collectors of said first and second transistors; a third transistor having a base electrode connected to said first input terminal and an emitter electrode connected to said base electrode of said second transistor; a fourth transistor having a base electrode connected to said second input terminal and an emitter electrode connected to said base electrode of said first transistor; and current supply means having first and second current input terminals connected to said collector electrodes of said first and second transistors, respectively, and first and second current output terminals connected to said emitter electrodes of said third and fourth transistors, respectively, for producing output currents at said first and second current output terminals in response to in put currents at said first and second current input terminals so that a ratio of said output currents at said first and second current output terminals is equal to a ratio of said input currents at said first and second current input terminals.
Claim 2
Dependent Claim
216 words
A differential amplifier arrangement comprising: first and second input terminals between which a signal source is connected; a differential amplifier circuit having first and second transistors, each having collector, base and emitter electrodes, said emitters of said first and second transistors being connected together, wherein an output voltage is derived from at least one of said collectors of said first and second transistors; a third transistor having a base electrode connected to said first input terminal and an emitter electrode connected to said base electrode of said second transistor; a fourth transistor having a base electrode connected to said second input terminal and an emitter electrode connected to said base electrode of said first transistor; and current supply means having first and second current input terminals connected to said collector electrodes of said first and second transistors, respectively, and first and second current output terminals connected to said emitter electrodes of said third and fourth transistors, respectively, for producing output currents at said first and second current output terminals in response to in put currents at said first and second current input terminals so that a ratio of said output currents at said first and second current output terminals is equal to a ratio of said input currents at said first and second current input terminals.
Claim 3
Dependent Claim
77 words
A differential amplifier arrangement according to claim 1, wherein said currently supply means comprises fifth and sixth transistors whose emitters are connected to said first and second current input terminals, respectively, and whose bases are connected to a reference voltage, and seventh and eight transistors whose collectors are connected to said first and second current output terminals, respectively, whose bases are connected to said second and first current input terminals, respectively, and whose emitters are connected together.
Claim 4
Dependent Claim
295 words
A differential amplifier arrangement comprising: first and second input terminals between which is signal source is connected; a differential amplifier circuit having first and second transistors, each having collector, base and emitter electrodes, said emitters of said first and second transistors being connected together; a third transistor having a base electrode connected to said first input terminal and an emitter electrode connected to said base electrode of said first transistor; a fourth transistor having a base electrode connected to said second input terminal and an emitter electrode connected to said base electrode of said second transistor; and current supply means having first and second current input terminals connected to said collector electrodes of said second and first transistors, respectively, and first and second current output terminals connected to said emitter electrodes of said third and fourth transistors, respectively, for producing output currents from said current supply means at said first and second current output terminals in response to input currents at said first and second current input terminals so that a ratio of said output currents at said first and second current output terminals is equal to a ratio of said input currents at said first and second current input terminals, wherein said current supply means further includes third and fourth current output terminals for producing output currents from said current supply means at said third and fourth current output terminals in response to input currents at said first and second current input terminals so that a ratio of said output currents at said third and fourth current output terminals is equal to a ratio of said input currents at said first and second current input terminals, wherein an output current is derived from at least one of said third and fourth current output terminals;
Claim 5
Dependent Claim
295 words
A differential amplifier arrangement comprising: first and second input terminals between which is signal source is connected; a differential amplifier circuit having first and second transistors, each having collector, base and emitter electrodes, said emitters of said first and second transistors being connected together; a third transistor having a base electrode connected to said first input terminal and an emitter electrode connected to said base electrode of said first transistor; a fourth transistor having a base electrode connected to said second input terminal and an emitter electrode connected to said base electrode of said second transistor; and current supply means having first and second current input terminals connected to said collector electrodes of said second and first transistors, respectively, and first and second current output terminals connected to said emitter electrodes of said third and fourth transistors, respectively, for producing output currents from said current supply means at said first and second current output terminals in response to input currents at said first and second current input terminals so that a ratio of said output currents at said first and second current output terminals is equal to a ratio of said input currents at said first and second current input terminals, wherein said current supply means further includes third and fourth current output terminals for producing output currents from said current supply means at said third and fourth current output terminals in response to input currents at said first and second current input terminals so that a ratio of said output currents at said third and fourth current output terminals is equal to a ratio of said input currents at said first and second current input terminals, wherein an output current is derived from at least one of said third and fourth current output terminals;
Claim 6
Dependent Claim
117 words
A differential amplifier arrangement according to claim 3, further comprising: a fifth transistor having a base electrode connected to said base electrode of said first transistor; and emitter and collector electrodes; a sixth transistor having a base electrode connected to said base electrode of said second transistor, and emitter and collector electrodes, said emitter electrodes of said fifth and sixth transistors being connected together; a seventh transistor having a base electrode connected to said first input terminals and an emitter electrode connected to said collector electrode of said fifth transistor; and an eighth transistor having a base electrode connected to said second input terminal and an emitter electrode connected to said collector electrode of said sixth transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-10 | 1992-10-10 | 1993-04-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-10 | 1996-10-10 | 1997-04-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-10 | 2000-10-10 | 2001-04-11 | $7700.00 | Window Closed / Lapsed |