US4081758A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low distortion signal amplifier arrangement
Assignee: RCA Corp
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Filing: 1976-05-27
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Granted: 1978-03-28
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Expires: 1996-05-27
Abstract
Abstract A signal amplifier arrangement comprises first and second differential amplifiers coupled in common to a current source which supplies all of the current to the amplifier circuits. Signals to be amplified are coupled between the control electrodes (bases) of the devices in each of the differential circuits by means of voltage follower stages. The main conduction path (collector-emitter) of each of the followers is coupled in series with the main conduction path of the device in the first differential circuit other than the one to the control electrode of which the follower output is coupled. Output signal current is produced in one or more load circuits connected to the second differential circuit, the output signal current being related to the differential input signal voltage but substantially independent of current level induced base-emitter voltage variations in the differential amplifier devices.
Inventors
- 👤 Steven Alan Steckler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 07:26
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F2203/00; H03F2203/45; H03F2203/45022; H03F2203/45612
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
247 words
A signal amplifier arrangement comprising: a first circuit path for providing a direct operating current; a first differential amplifier circuit comprising first and second semiconductor devices, each having a main current conduction path coupled to said first direct current circuit path and each having a control electrode; an output differential amplifier circuit comprising third and fourth semiconductor devices, each having a main current conduction path coupled to said first direct current circuit path and each having a control electrode direct current coupled respectively to control electrodes of said first and second devices; at least a first output load circuit coupled to a main current conduction path of one of said third and fourth devices at a point remote from said coupling to said first direct current providing circuit path; a source of signals to be amplified; means comprising fifth and sixth semiconductor devices having main current conduction paths coupled respectively to said main current conduction paths of said second and first devices, having conduction characteristics substantially equal to conduction characteristics of said first and second devices and each having a control electrode coupled to said source of signals for coupling signal voltages between said control electrodes of said first and second devices and between said control electrodes of said third and fourth devices; whereby output signal current produced in said load circuit is related to said signals and substantially independent of current level induced variations in characteristics of said devices to which said signal voltages are coupled.
Claim 2
Dependent Claim
247 words
A signal amplifier arrangement comprising: a first circuit path for providing a direct operating current; a first differential amplifier circuit comprising first and second semiconductor devices, each having a main current conduction path coupled to said first direct current circuit path and each having a control electrode; an output differential amplifier circuit comprising third and fourth semiconductor devices, each having a main current conduction path coupled to said first direct current circuit path and each having a control electrode direct current coupled respectively to control electrodes of said first and second devices; at least a first output load circuit coupled to a main current conduction path of one of said third and fourth devices at a point remote from said coupling to said first direct current providing circuit path; a source of signals to be amplified; means comprising fifth and sixth semiconductor devices having main current conduction paths coupled respectively to said main current conduction paths of said second and first devices, having conduction characteristics substantially equal to conduction characteristics of said first and second devices and each having a control electrode coupled to said source of signals for coupling signal voltages between said control electrodes of said first and second devices and between said control electrodes of said third and fourth devices; whereby output signal current produced in said load circuit is related to said signals and substantially independent of current level induced variations in characteristics of said devices to which said signal voltages are coupled.
Claim 3
Dependent Claim
56 words
An arrangement according to claim 1 wherein: said first, second, fifth and sixth devices are like conductivity transistors, said control electrodes are base electrodes and said main conduction paths are between respective collector and emitter electrodes; and said fifth and sixth transistors are coupled in emitter follower configuration with respect to said signals to be amplified.
Claim 4
Dependent Claim
37 words
An arrangement according to claim 2 wherein: said collector-emitter paths of said first and sixth transistors are coupled in series combination and said collector emitter paths of said second and fifth transistors are coupled in series combination.
Claim 5
Dependent Claim
25 words
An arrangement according to claim 3 wherein: said transistors in each said series combination carry like quiescent currents and thereby have like base-emitter offset voltages.
Claim 6
Dependent Claim
23 words
An arrangement according to claim 4 wherein: output voltage across said output load circuit is substantially free of base-emitter offset voltage distortion effects.
Claim 7
Dependent Claim
47 words
An arrangement according to claim 5 and further comprising: a second output load circuit coupled to a main current conduction path of the other of said third and fourth devices, whereby output voltage across said second load circuit is substantially free of base-emitter offset voltage distortion effects.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-03-27 | 1981-09-26 | 1982-03-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-03-27 | 1985-09-26 | 1986-03-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-03-27 | 1989-09-26 | 1990-03-28 | $7700.00 | Window Closed / Lapsed |