Crosspoint switching array

Claim 2

A crosspoint switching array for connecting any one of a plurality of M input ports to any one of a plurality of N output ports including M x N crosspoint switching means arranged in M rows by N columns, each crosspoint switching means comprising a row input connection and a row output connection, the row input connection being connected to the row output connection of the preceding crosspoint switching means in the row, and the row output connection being connected to the row input connection of the following crosspoint switching means in the row; a column input connection and a column output connection, the column input connection being connected to the column output connection of the preceding crosspoint switching means in the column, and the column output connection being connected to the column input connection of the following crosspoint switching means in the column; row buffer means having an input connected to the row input connection and an output connected to the row output connection; selector means having a first input connected to the column input connection, a second input connected to the row output connection, an output connected to the column output connection, and control input means; said selector means being operable in response to a first control condition at the control input means to provide a closed circuit condition between the first input and the output thereof and an open circuit condition between the second input and the output thereof; and said selector means being operable in response to a second control condition at the control input means to provide an open circuit condition between the first input and the output thereof and a closed circuit condition between the second input and the output thereof.

Claim 3

A crosspoint switching array in accordance with claim 1 wherein said selector means includes first switching means having an input connected to the fist input of the selector means and having an output; second switching means having an input connected to the second input of the selector means and having an output; column buffer means having an input connected to the outputs of the first and second switching means and having an output connected to the column output connection; said first switching means being coupled to said control input means; said first switching means being biased in a closed condition when the first control condition is present at said control input means, and being biased in an open condition when the second control condition is present at said control input means; and said second switching means being coupled to said control input means; said second switching means being biased in an open condition when the first control condition is present at said control input means, and being biased in a closed condition when the second control condition is present at said control input means.

Claim 4

A crosspoint switching array in accordance with claim 2 wherein said row buffer means includes driver circuit means for producing a first predetermined voltage level at the output thereof in response to a digital signal of one binary value at the input thereto and for producing a second predetermined voltage level at the output thereof in response to a digital signal of the opposite binary value at the input thereto; and said column buffer means includes driver circuit means for producing said first predetermined voltage level at the output thereof in response to a digital signal of said one binary value at the input thereto and for producing said second predetermined voltage level at the output thereof in response to a digital signal of said opposite binary value at the input thereto.

Claim 5

A crosspoint switching array in accordance with claim 3 wherein said driver circuit means of said row buffer means includes a row inverter circuit of a first row buffer transistor connected between a source of operating potential and said row output connection and a second row buffer transistor, complementary to said first row buffer transistor, connected between said row output connection and a point of reference potential, said first and second row buffer transistors each having a control electrode connected to said row input connection; and said driver circuit means of said column buffer means includes a column inverter circuit of a first column buffer transistor connected between a source of operating potential and said column output connection and a second column buffer transistor, complementary to said first column buffer transistor, connected between said column output connection and a point of reference potential, said first and second column buffer transistors each having a control electrode connected to the outputs of said first and second switching means.

Claim 6

A crosspoint switching array in accordance with claim 4 wherein said first switching means includes a first column switching transistor connected between said column input connection and the control electrodes of the first and second column buffer transistors and a second column switching transistor, complementary to said first column switching transistor, connected between said column input connection and the control electrodes of the first and second column transistors in parallel with said first column switching transistor; said second switching means includes a first row switching transistor connected between said row output connection and the control electrodes of the first and second column buffer transistors and a second row switching transistor, complementary to said first row switching transistor, connected between said row output connection and the control electrodes of the first and second column buffer transistors in parallel with said first row switching transistor; said first column switching transistor and said second row switching transistor being complementary transistors and each having a control electrode connected in common to a first control input connection; said second column switching transistor and said first row switching transistor having complementary transistors and each having a control electrode connected in common to a second control input connection; said first and second column switching transistors being biased for conduction therethrough and said first and second row switching transistors being biased to nonconduction when a first voltage level is present at said first control input connection and a second voltage level is present at said second control input connection; and said first and second row switching transistors being biased for conduction therethrough and said first and second column switching transistors being biased to nonconduction when said second voltage level is present at said first control input connection and said first voltage level is present at said second control input connection; whereby when said first voltage level is present at said first control input connection and said second voltage level is present at said second control input connection, digital signals present at said row input connection are coupled to said row output connection and digital signals present at said column input connection are coupled to said column output connection; and whereby when said second voltage level is present at said first control input connection and said first voltage level is present at said second control input connection, digital signals present at said row input connection are coupled to said column output connection.